SoCs face challenges on integration road
EE Times: Latest News SoCs face challenges on integration road | |
Gene Frantz and Thanh Tran (03/29/2004 6:00 AM EST) URL: http://www.eetimes.com/showArticle.jhtml?articleID=18401698 | |
The idea of a true system-on-chip has been the semiconductor industry's holy grail for three decades. Much has been accomplished and more remains to be done.
Fabricating analog and RF with digital circuits is the real challenge because it requires different IC processes. Analog, digital and RF integration is a reality — Bluetooth chips are good examples. But these are custom designs in which the analog and RF circuits are relatively unsophisticated compared with the ultimate desire for a system-on-chip.
Given that chip integration remains elusive, it is useful to define another concept: the discrete SoC, which is a system on its way to the final integration. The concept helps chip architects and designers implement interim integration steps with the final goal in mind.
The discrete SoC concept is embodied in the chip sets for personal video recorders (PVRs), with large blocks of high-speed digital circuits, BiCMOS audio and video codecs, and TV tuners that use relatively exotic fabrication technologies. The progress of PVRs provides an example of the integration steps of such a complex system.
The challenges presented by discrete SoCs, however, are so daunting that some commonly held ideas about the benefits of integration — smaller, faster, cheaper — may prove invalid as the industry approaches the final integration.
In the context of a true SoC, a single device does not guarantee the lowest system cost, highest performance or lowest power dissipation. And although it is most likely to provide a smaller size, it seldom makes sense to sacrifice cost and power for size.
In 2000, a typical PVR system consisted of eight chips. Knowing that integration is an incremental process and that board-level solutions will continue through 2006, design teams can develop new generations by following four basic rules. And, of course, this will make each successive integration easier and faster.
Some mismatches Digital-processing units could quickly come together into a single CMOS chip, while the BiCMOS audio codec, video encoder/decoder and TV tuner were not candidates for integration in 2002 because of fabrication technology mismatch.
The oversampling audio codec could be fabricated in CMOS, but in this scenario it is not. Integrating the audio codec with the CPU and MPEG can degrade audio quality — a difficult design problem.
The video encoder and decoder use BiCMOS technology and can be integrated into a single chip. This will occur in 2004. Although the TV tuner uses BiCMOS technology in the 2002 generation, it switches to silicon germanium in the 2004 generation when the video encoder/decoder are on a single BiCMOS chip.
Fabrication technology and the hardware components it produces pose big challenges, but are not the most daunting on the horizon for SoCs. An electronic system can be viewed as having five building blocks: manufacturing, hardware components, operating system, application-specific software and development environment.
Digital chips today require large verification teams, complex software, expensive hardware in the form of emulators — and many months of development. The addition of analog and RF will spin the problem out of control.
Gene Frantz, above, is principal fellow and Thanh Tran is senior member of the technical staff at Texas Instruments Inc. (Dallas).
| |
All material on this site Copyright © 2005 CMP Media LLC. All rights reserved. Privacy Statement | Your California Privacy Rights | Terms of Service | |
Related Articles
- Opportunities and Challenges for Near-Threshold Technology in End-Point SoCs for the Internet of Things
- Safety in SoCs: Accelerating the Road to ISO 26262 Certification for the ARC EM Processor
- Challenges in verifying PCI Express in complex SoCs
- Road to Auto Market Paved With Fault-Tolerant SoCs
- A framework for the straightforward integration of a cryptography coprocessor in SoC-based applications
New Articles
Most Popular
- Streamlining SoC Design with IDS-Integrateâ„¢
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- PCIe error logging and handling on a typical SoC
E-mail This Article | Printer-Friendly Page |