DSP-Free, WiFi Handset Could Unlock VoIP Market
EE Times: Latest News DSP-Free, WiFi Handset Could Unlock VoIP Market | |
Eric Fujishin and Chip Stearns (05/03/2004 6:00 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=19400013 | |
Over the last year, interest in voice-over-Internet Protocol (Vo-IP) service has seen a resurgence. Still, one barrier to widespread adoption has been the cost of the handset; one way through that barrier is wireless fidelity (WiFi) VoIP using a single RISC processor. Indeed, WiFi could be the technology that drives VoIP into every home and office if a low-cost handset is built around a single RISC based system-on-chip, eschewing a separate digital signal processor (DSP). The savings in the bill of materials could well drive what has been a market kept stagnant by high-cost handsets.
Few disagree that making telephone calls over the Internet is compelling and inevitable. Perhaps it is the sudden endorsement by major phone carriers like AT&T, France Telecom, T-Mobile, Sprint and Verizon. Or perhaps it is the noticeable success of Cisco in the enterprise, or of Vonage in the home. Or is it the rapid inclusion of VoIP into access points, DSL modems, cable modems, set-top boxes and gateways? Probably it's all of the above.
Most VoIP calls can be carried over wireless LAN handsets. They resemble a cordless or cellular phone, but have the convenience, access and ability to place a call around the world at a fraction of today's cost. These voice-over-WLAN (VoWLAN) handsets can operate with all WLAN access points and feature extended battery life, quality of service and security. But most important, these headsets carry a very low price.
To that end, a few companies are developing and licensing hardware and software technology to enable the low-cost VoWLAN handsets. A block diagram of one (see figure) lacks a DSP because next-generation DSP software, including all the required voice codecs, framework and protocols, can be ported onto a single RISC processor. Even the WLAN functionally can be executed in software on the RISC processor. The resulting small die size halves the cost of a comparable chip needing a DSP, thereby reducing the handset cost.
For example, a main system CPU controller like the ARM968E-S, optimized for minimal die size (almost that of an ARM7) and very fast interrupt response time can maintain the high performance of an ARM9-class processor. This processor provides dual Advanced High-Performance Buses-lite (AHB) and a dual-banked-data tightly coupled memory (TCM), in which one bank contains even addresses, the other odd addresses. This arrangement allows an independently functioning DMA to access one bank of data from the TCM while the processor core accesses the other bank, provided that both are simultaneously operating on sequential addresses. Because the accesses alternate between odd and even addresses, both DMA and CPU accesses can simultaneously run at full speed.
The AHB-lite buses--one dedicated to DMA and the other to system peripherals--in conjunction with the dual-banked-data TCM, play a critical role in erasing the delays typically created by single-bus data processing. Contention issues, like interrupts, occurring during DMA are minimized, which allows the VoIP software to make efficient use of available CPU cycles. The result is the ability to run the VoIP codec, protocols and WLAN media access control (MAC) all on the same processor.
The marriage of the increasing capabilities of the RISC processor with the small-footprint implementations of complex DSP algorithms yields the first ever single-chip and DSP-free VoWLAN device: the ARM968E-S. Built using a 0.13-micron process, the device runs at more than 200 MHz. Because the VoIP software needs 60 MHz and the WLAN MAC software needs 30 MHz, the total VoWLAN function takes less than half of the available peak processing power.
The part of WLAN technology that does not lend itself to CPU processing is the convolution coder and the encryption engine. These bit- (rather than byte- or word-) oriented operations are best relegated to Advanced High-Performance Bus peripheral devices like low-bit-rate (LBR) physical layer and the Automatic Error Cancellation (AEC) engine. The LBR PHY and the AEC consist of only two 12,000-gate Advanced Microcontroller Bus Architecture peripherals.
To be sure, the instantiation of VoIP and WLAN in software on a RISC processor is not enough to qualify as a VoWLAN solution. As many users are painfully aware, WLANs drop packets, which has a devastating affect on a transmitted voice stream. In fact, it is not uncommon for a WLAN access point to lose 30 percent of its packets. For data packets that are insensitive to time, the WLAN user need only wait a few more seconds and barely notices the problem. But when the user loses voice packets, the clicks, pops and ticks make the VoWLAN call incoherent.
Therefore, drastic improvements are needed in techniques that conceal packet losses. Simply buffering large numbers of voice packets to buy time for retransmission does not solve this quality-of-service problem. These techniques only add latency to the voice call and make it difficult to carry on a conversation. Rather, new techniques are needed that interpolate between successfully received packets to psycho-acoustically create the least annoying and distracting audio sample. Such technology is tightly coupled in software to the voice engine running on the processor.
Also, while the vast majority of WLAN access points in operation today do not encrypt data, a VoWLAN phone call will require security. People expect privacy and strong encryption is a market enabler. Toward that end, 802.11i, specifically Advanced Encryption Standard (AES), is sufficient to satisfy both the reality and perception that a conversation cannot be overheard. Therefore, an AES function is included in the block diagram as a peripheral device and made available to the CPU as the WLAN software is parsing each frame.
VoWLAN handset manufactures may want to instantiate different encryption (WEP, TKIP, or proprietary) schemes, as their market requires. For that reason, the encryption peripheral is a memory-mapped device that not only offloads the encryption computation from the processor, but abstracts that function so that other encryption engines can be instantiated without having to change the underlying hardware of the software architecture.
Eric Fujishin (eric.fujishin@arm.com) is the worldwide networking segment manager at ARM Inc. (Carlsbad, Calif.). Chip Stearns (chip@hellosoft.com) markets SoC platform IP products, including VoWLAN and Cellulan, for HelloSoft Inc. (San Jose, Calif.).
| |
All material on this site Copyright © 2005 CMP Media LLC. All rights reserved. Privacy Statement | Your California Privacy Rights | Terms of Service | |