Developing an ATE strategy for PCI Express

With the introduction of PCI Express into the mainstream PC market, IDMs and fabless companies now face a new breed of test challenges. The demands of testing this next generation, high speed IO protocol, predominantly found in the datacom market, are requiring these companies to develop new production test strategies, beginning with an assessment of their pre-production characterization efforts to determine what tests need to be carried into the production phase.

They must then consider the anticipated test costs of the production phase"a critical factor in determining the viability of any test strategy. In order to capitalize on the competitive market for PCI Express-enabled devices, IDMs and fabless companies need to determine how to rapidly implement a cost-effective production test strategy that does not compromise their device quality.

The SERDES challenge

PCI Express enables higher bandwidth inter-chip communication, relying on SERDES technology to provide a new high speed IO between the various PC support chips. SERDES testing requires full analysis of the transmit and receive pins of the device under test. But with the mainstream introduction of PCI Express, the additional challenge of high volume production test requirements must now be considered. SERDES testing alone is insufficient to develop a high yielding production test strategy that aligns with the cost sensitivity of the end application market.

PCI-SIG, a Special Interest Group that owns and manages PCI specifications as open industry standards, has drafted a document outlining 31 tests for PHY compliance and performance. Addressing 60 test assertions consisting of five sections"General, Transmitter, Receiver, System board and Add-in Card, this document provides a good starting point for silicon-level characterization, although many of the tests focus on system-level performance of the devices. For production test, there are opportunities to prioritize the tests selected from this document and to add additional tests that will better align with the end goal of cost effective, high yield test strategy.

In addition to SERDES requirements and the PCI-Express focused tests outlined by PCI-SIG list, the following requirements must also be taken into account when developing a test strategy:

*Other buses on the device must be able to support a greater level of data transfer.
Depending on the end user application for the device, these IO pins could be high speed, parallel source synchronous bus architectures. These types of interfaces require vector-based testing to test the IO functionality of the pins.
*Pins must be able to send and receive scan data.
As the core of the devices using PCI Express I and O will typically have high transistor counts, the ability to send and receive scan data through standard, and potentially the PCI Express pins, must be considered.

*Third-party IP can be used to implement PCI Express SERDES capability.
Many of the high speed IO cells utilized in these designs will be available from third-party IP companies. In many cases, these IO designs will include BIST engines, such as on-chip PRBS generation and signature capture, to enhance testability. Any test strategy should look to see how to take advantage of these designs in production.

Preparing for production test

In the characterization phase, much of the effort is directed at completely analyzing the performance envelope of the SERDES designs. Tx and Rx jitter analysis must be performed, plus validation of compliance to the full PCI Express feature set. However, some of the instrumentation that may be used in the characterization phase, e.g. PRBS/BERT analyzers, will not have the appropriate level of scalability in terms of multi-site test, nor meet the throughput requirements demanded for high volume production test.

Further, some characterization solutions will be unable to test other sectors or blocks of the PCI Express device. So, in order to meet the cost and quality targets for your devices, the following areas should be considered and prioritized.

As stated previously, the PCI-SIG document outlines 31 tests. Of these, 14 have been identified as lead indicators of silicon-level performance. In addition, LTX has identified three additional tests based on its datacom test experience that should be included in any test list. The emphasis of these tests is to:

*Enable full monitoring of the Tx pins jitter content.
*Provide max/min limits testing to stress Rx pins sensitivity to voltage and jitter extremes.
*Identify voltage characteristics of the differential signals.
*Enable lane-to-lane timing.

Further analysis will be required to determine how much of the above can be tested or validated using loopback techniques and any on-chip BIST. However, due to the high sensitivity of jitter to process variations (including fabrication, assembly and packaging), any production test solution must provide an "opening" of the loop to enable separate analysis of Tx and Rx pins to determine the root cause of any yield dropout. These tests will likely come from the 17 different tests identified above and will be included in any production test plan. These tests will have the option to be turned on/off as the production data collection indicates.

Define Non-SERDES test requirements

In addition to the SERDES-oriented tests, it is important to define what other test capabilities are required at the PCI Express I and O pins. Ideally, all of these capabilities can be switched within the ATE itself and not require complex, fragile load board designs. Examples of the types of tests required here are: DC measurements to check for correct voltage, current and impedance characteristics; receiving and driving of scan vectors; and parallel digital vectors.

All of these features are freely available on standard digital ATE pins, but are not normally available in instruments designed to test the timing and jitter content of SERDES pins.

To support the non-SERDES pins on the device, you must also ensure that the test capability of the manufacturing test solution can support the functionality of the rest of the device, for example: high speed, synchronous bus architectures running up to and beyond 1.0Gbps; bus to test on chip memory or gain access to on-chip MBIST; and a mix of differential and single ended pins.

Once again, many of these features are available on more recent ATE platforms. However, this capability is not necessarily "integrated" with the SERDES test capability. The next section will look at what "integration" fully entails when thinking in terms of a production test solution.

Selecting the production test platform

Clearly there are many variables to consider when selecting a test platform for a high-yielding production PCI Express test strategy. To address these variables, a test solution should be fully integrated and provide scalability in terms of configurability and capability.

The platform must also have the architecture and instrumentation flexibility to support characterization and fast track to production. This includes having a universal pin structure that enables switching of: DC features, scan data, digital data, PRBS data sequences, jitter injection, time domain waveform analysis, loopback modes to enable device Tx to Rx connections, and high bandwidth connection to TIA resources.

In addition, the platform must allow test resources to be cost-effectively scaled to enable multi-site testing. Test options must be able to support multi-parallel and parallel multi-lane testing. By integrating all the required functionality behind the universal pin structure load board, designs become simplified and therefore more scalable.

The test platform must also offer a software environment that enables the addition/removal of test blocks to meet the turn on/turn off requirements outlined in the previous section. Further, this test environment must provide a range of tools that simplify the task of debugging and analyzing the multi-time, multi-function applications. It must also provide suite of data collection and analysis tools that aid in the task of yield monitoring and improvement.

As PCI Express becomes more ubiquitous in next-generation devices, IDMs and fabless companies are now challenged with developing viable production test strategies that balance performance with test economics. Though undeniably a critical factor, SERDES testing alone is just one component of the test requirements. An effective production test strategy for PCI Express devices must ensure complete coverage across the device, and utilize an ATE platform that provides the right capabilities, scalability and flexibility. In this way, device quality can be ensured and optimum test economics can be achieved.