'Symmetric' design technique facilitates power analysis

These changes give rise to powerful transients in on-chip, package and board level power grids. Careful power planning is necessary to reduce these transients, which otherwise can cause timing errors, increased stress in thin gate oxides, and circuit failure.

Power supply-related noise coupling is very hard to analyze using traditional circuit simulation techniques such as Spice. The size of the netlist required to simulate a multi-chip system, and the analysis of the complex multiple couplings between power supply and signal nets, have prevented proper simulation-based power grid design.

Designers thus have to rely on layout extraction techniques followed by static or restricted dynamic analysis of parts of the system. As we will see, this is a dangerous approach to high-speed power network design. Complex interactions between different parts of the system give rise to local power supply variations related to the clock frequency and global transients related to the geometry of the system level power network.

This paper describes a design technique and simulation methodology which allows the simultaneous analysis of all chip, package and board level components. By separating the power net into a global net and a local net, the problem can simplified to the point where simulation run times can be reduced by many orders of magnitude. In the global net, most of the energy is stored in the magnetic field and dissipated as heat; in the local net, almost all of the energy is stored in the electric field. These techniques also have the advantage of reducing unwanted radiation and coupling between power and signal nets.

Symmetry in high-speed power networks

Figure 1 shows some of the components in a high-speed system level power network designed using a technique based on symmetric transmission line pairs. A key component is the on-chip global power distribution grid.

This is a two layer symmetric grid constructed using an array of closely spaced transmission line pairs. The wires in each power/ground pair are placed at or near the minimum design space to minimize inductance and maximize capacitance in the global grid. The designer connects all active and inactive (de-cap) circuits to this grid using an array of short vertical wires (vias).

Figure 1 — Components in a system-level power network

If enough of these connections are made, then all resistive and inductive voltage drops in the vertical direction are small enough to ignore (the typical distance to all other wiring layers in the IC is no more than a few microns). This also ensures that all voltage drops in horizontal wires in all other layers are small enough to ignore.

Under these conditions all on-chip supply voltage drops and increases are caused by horizontal current flow in the global two-layer grid. This means that is not necessary to simulate an RLC network for all layers in each IC. The effect of decoupling capacitance needs to be included for all layers. Energy storage in the magnetic field (inductance) and energy dissipation as heat (resistance) only needs to be calculated for the global grid.

Connection symmetry is just as important as routing symmetry. Figure 2 illustrates the importance of connection symmetry in high-speed power networks. Connecting the current source to the global grid at point A rather than point B ensures that voltage and current waves are equal in magnitude and have opposite signs in supply and return nets.

Equal and opposite currents in closely spaced transmission line pairs have the advantage of minimizing unwanted magnetic coupling between the power supply and other networks. This symmetry also means that it is not necessary to calculate power noise on both rails.

We can simulate one rail only using a single uncoupled partial differential equation (Figure 3). Current supplied to active devices in the chip can be modeled using a distributed current source. A single current profile is used for each circuit block (obtained from a transistor or gate level simulation).

Figure 2 — Symmetric connections to the on-chip power grid.

The "block" could represent the current sourced by a single transistor or gate, but this level of detail is usually not necessary for power grid analysis. Worst-case power noise occurs when large numbers of closely spaced gates switch simultaneously, or circuit blocks are switched on and off for power saving.

Each current source is distributed uniformly across a circuit block area. This approximation is valid for a block that is well connected; that is, a block that has many (symmetric) tap points distributed uniformly across the area occupied by the block. Decoupling capacitance is also distributed uniformly across each block area. Dividing each transmission line pair into short elements, the voltage change across and current through each element is given by:

where dx is the length of the element, w is the wire width, R_s is the sheet resistance, L is the inductance per unit length of the wire, I₀ is current per unit length and C is capacitance per unit length.

Simulation examples

Figure 4 shows simulation results for a single IC containing a single active dynamic current source and ideal voltage sources at the chip boundary. The result is from the Picosim tool from Quantum Design Automation. This type of simulation can be used to get a quick estimate for on-chip grid dimensions and decoupling capacitance before running a complete system level simulation, and takes only a few seconds to run on a typical workstation.

This illustrates the main advantage of this type of symmetric design. Entire power distribution systems containing multiple ICs can be simulated over many clock cycles in a few hours using standard, off-the-shelf hardware.

The IC is 4x4mm in size. Each transmission line pair in the two-layer global on-chip grid has 10um wide, 20mOhm/sq wires, and each pair is spaced periodically at 80um. The inductance per unit length of each transmission line pair is 10nH/cm and the IC has a uniform de-cap per unit area of 5nF/cm².

On and off chip decoupling capacitance are important parameters in any high speed power noise simulations. These can be obtained using an extraction tool, or estimated from the number of transistors/gates and the wire density within a specified region. In a more realistic example, a number blocks of varying size and capacitance would be defined in different regions of the IC to study the effect of on-chip de-cap on noise level and distribution.

Note that this capacitance is the total capacitance between power and ground nets within the defined region. It includes all parasitics from all layers, and any de-cap added intentionally by the designer. A simple linear ramp is defined for a single active current source in a small region of the IC. All other circuits are assumed to be switched off.

Figure 4 — Picosim result for a single IC and ideal voltage sources.

Note that inductance dominates voltage drop and ground bounce at high frequency (dI/dt). The voltage wave front propagates out from the current source at a velocity given by:

where s is the periodic distance between transmission line pairs in the on-chip grid, L is inductance per unit length, and CA is the capacitance per unit area in the region surrounding the source. These results also show clearly the effect of minimizing inductance by reducing the space between power and ground wires in each transmission line pair. This is not necessary at low frequency where, as the graph shows, we get a frequency independent IR drop and ground bounce.

What goes up must eventually come back down again. Figure 5 shows a result using a more realistic gate switching profile. This plot is output by an on-chip electromagnetic field solver and shows the maximum and minimum supply voltage change (delta[Vdd-Gnd]) across the chip surface.

As the current ramps down, the energy stored in the magnetic field surrounding on-chip power grid wires is returned to the grid, causing an increase in supply voltage. This energy is, of course, available to power active circuits during subsequent clock cycles but it is not always available at the place and time you need it!

Supply bounce (Vdd up, Gnd down) can cause damage to thin dielectrics, particularly if it is already close to its specified maximum value for high speed operation. It also contributes to timing variations. Supply bounce can also be caused by resonance in the on-chip grid, package and elsewhere. All of these effects can be studied in detail with short simulation times using symmetric transmission line techniques.

In these simple examples, any energy which is not dissipated as heat in the on-chip grid is reflected from the ideal voltage sources at the chip boundary. When the IC is connected to the package and board level power network the results can be very different. These long transmission lines have much greater inductance and can give rise to powerful system level transients when blocks are switched in and out during normal IC operation.

The system illustrated in figure 6 includes a package grid and 5 long board level connections to the power supply. The average current consumption of all active current sources in this simulation is 1.43A. A simple static analysis using this current distributed uniformly across the chip surface gives 29.5mV maximum IR drop. Figure 7 shows what happens when all the current sources shown are clocked at 2.5GHz at time t=0.

The peak frequency of this noise can be calculated from the resonant frequency of the series combination of the total on-chip capacitance and the external inductance. It takes approximately 300 clock cycles for this system level transient to die out.

Clearly, measures have to taken to suppress these transients. For example, using ideal or non-ideal decoupling capacitors (on or off chip), reducing the distance between the power supply and IC, or using additional connecting transmission lines. Adding connections will reduce the amplitude of the global transient but will also increase the system Q, causing it to ring for longer, unless the wires are made more resistive.

Note the symmetry between voltage changes in supply and return nets. This is a direct consequence of the geometric and connective symmetry of the transmission line pairs in the layout. The currents at each node are also symmetric. This results in most of the electromagnetic energy associated with the power noise being confined to the narrow gap between wires in each transmission line pair.

This guided wave approach to power grid design minimizes unwanted coupling to other nearby nets. The translational and rotational symmetry of the two layer global on-chip grid provides additional advantages when devising efficient numerical schemes for solving the transmission lines. A 250 clock cycle simulation of this entire system takes less than one hour on a standard, single processor workstation.

These results are valid when there is sufficient margin between the noise level and supply voltage. For low supply voltages, the large supply voltage drop and ground bounce as the on-chip de-cap discharges at the start of the simulation will reduce transistor currents across the chip surface (it is some time later before current from the power supply reaches the chip). This negative feedback on the current sources will reduce the noise magnitude seen here, but not before complete circuit failure.

Conclusion

A design methodology and simulation technique based on transmission line pairs and connection symmetry has been described. These methods make multiple IC, package and board co-simulation of power networks possible using standard computing hardware. Power supply problems such as on and off chip supply drop/bounce, resonance and wave propagation can be analyzed in multi-chip systems with realistic simulation times.

Donald Bennett is a device physicist and IC design engineer, formerly of ST Microelectronics in the U.K. Previous publications include articles on radiation related-defects in semiconductors and IC power noise. He now develops and markets the system level power planning and analysis tool Picosim at Quantum Design Automation.