Trade-offs in high-performance comms

Designers seeking to integrate high-performance communications systems historically have opted to implement increasingly larger portions of their designs into either ASICs or FPGAs. But the recent emergence of structured ASICs has developers taking a new look at the traditional issues driving the use of FPGA or ASIC technology for silicon integration.

For communications equipment, performance is a given. Line cards must provide the full line-rate performance and the throughput needed to support the high-speed backplanes employed on today's dense switching platforms. In addition, line cards must add the computational resources required to enable capabilities such as line-rate forwarding with access control lists (ACL), quality-of-service (QoS) and rate limiting.

The Gigabit Ethernet line card is an example of the challenges designers face in density and throughput. The performance requirements play a pivotal role in the decision process for design teams weighing an FPGA- or structured ASIC-based solution. Today's structured ASIC solutions fabricated in a 0.13-micron process could support the 10-Gbit/second data rates, while emerging 90-nanometer technologies will support significantly higher performance.

Theoretically, a design team could implement multiple serial I/Os with 2.5 Gbit/s data rates in a single FPGA as well. But the inherent limitations of a programmable-logic architecture would force designers to use three to four times the logic of a structured ASIC and, in the process, drive the cost of the FPGA prohibitively high.

Another option to consider is to integrate the design into a smaller FPGA and a standard off-the-shelf ASSP. Given that the integration of all four functions might exceed the logic capacity of a single FPGA, this approach would let the designers use a smaller, more affordable FPGA and address functions such as the backplane interface with an ASSP.

Logic capacity
Intrinsic to the discussion of performance capabilities is the logic capacity of each technology. In the Gigabit Ethernet line card, the PHY, the link implementation including a gigabit media access control (MAC) for eight channels, and the serial backplane interface would require 400,000 to 500,000 gates of logic. If the design was implemented in a structured ASIC design with more than 1 million ASIC gates in a 0.15-micron process-which is available today-that would leave more than 500,000 gates of logic running at 200 MHz to implement the highly complex local switch/security engine.

To achieve a similar design in a lower-performing FPGA would require a device with at least 2 million to 3 million gates of logic. This level of logic integration is beyond the capacity of today's FPGAs. It could be done by breaking up the design into multiple FPGAs, but that would raise issues of design partitioning, system footprint and power consumption.

One of the most attractive advantages of an FPGA-based solution is its fast turnaround. Designers can program the chip in days and don't have to wait for chip fabrication. By having some of the preconfigured logic, memory and I/O embedded in the device, structured ASICs have drastically shortened the typical five- to six-week fab cycle of traditional standard cell-based ASICs.

But, in a high-performance line card design, the advantages of an FPGA may not be as dramatic. The packet-oriented nature of this design implies the constant shuffling of data traffic from line to memory and back, and to the switch fabric and back, requiring the allocation of at least two major time domains within the chip. As designers push the performance of FPGAs, closing timing on a design in an FPGA architecture where the structure of the clock is not well-defined will pose a tough task. This process likely will require multiple design iterations.

Designers using a structured ASIC, on the other hand, have at their disposal clock domains already embedded in the metal layer of the chip structure. Since speed, propagation and delays are pre-defined, and since the structured ASIC offers higher performance, designers can implement the design with wider margins and are more likely to build a viable solution in a single pass.

Power concerns
Power consumption is a major concern in any high-performance communications application. As designers push the density of switch designs, power, and its implications for system noise and thermal management, have become a problem.

For this design requirement, structured ASICs offer a more highly optimized solution than a single FPGA or combined FPGA/ASSP implementation. Designers typically use logic blocks less efficiently in an FPGA than in a structured ASIC.

In recent years, as NRE and mask costs have skyrocketed, this issue has kept many designers from taking advantage of standard-cell technology. By having some of the logic, memory and I/O preconfigured in the device, structured ASICs offer much lower up-front costs than a traditional standard-cell design.

Unlike FPGAs, however, structured ASICs still require an up-front NRE cost, with most ranging from $60,000 to $200,000. The NRE expenses associated with a structured ASIC design will be mitigated, however, by significantly lower unit prices. The high-density FPGAs required for this application sell at per-unit costs in the hundreds or thousands.

While most line card applications reach midvolume levels of production, the dynamic nature of the communications market leaves open the possibility that a design initially targeted for production in the 10k- to 20k-unit range may some day find demand at high enough volumes to justify the NRE costs associated with cell-based ASICs. Although the process of migrating from programmable logic to an ASIC implementation exists, design teams still face multiple obstacles. First, the designer must requalify all the IP blocks used in the FPGA implementation to build an ASIC. Second, the design team must quickly familiarize itself with a distinctly different ASIC development flow.

Design teams using structured ASICs do not face the same obstacles. The re-qualification of IP is generally not an issue since the most challenging part of the design can be derived directly from the company's cell-based ASIC library. Therefore, designers migrating from a structured ASIC to a standard cell-based ASIC have at their disposal a silicon-proven solution.

Vadim Shain (cc.shain@necelam.com) is a systems application engineering manager and Steven Kawamoto (cc.kawamoto@necelam.com) is senior marketing manager at NEC Electronics America Inc. (Santa Clara, Calif.).

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