IP reuse simplifies SoC design, verification

Larger, more-complex digital designs demand inventive techniques and tools that simplify the design and verification process. This is a response to both design complexity challenges and the new opportunities of increased silicon real estate. For example, at this year's Design Automation Conference, Gary Smith of Dataquest observed that the advent of 65-nanometer processes marked the first time that system developers were unable to use all of the available design gates. This gap between fabrication and design potential has been recognized by the EDA industry, which has been hard at work on various strategies to close it. One of the most promising is the automated integration of intellectual property (IP) using a platform-based design strategy.

The current, popular design approach, which generally consists of top-down synthesis, software simulation and limited design reuse, is not keeping pace with Moore's Law, which is equivalent to a 59 percent growth rate. In 1994, a 100,000-gate design would consume an area roughly measuring one-quarter of a square centimeter. Today a 305,000-gate design consumes only one-tenth of a square centimeter. Conversely, design productivity has increased by roughly 25 percent per year. There is a growing gap between what can be designed and what can be manufactured. This creates a situation that will trigger a design paradigm shift and create a strategic inflection point for the electronics industry.

Fill available gates
There are several approaches to closing the design potential gap, each with its own strengths and weaknesses. The approaches are IP reuse, high-level design and behavioral synthesis, software (CPUs and memory) and replication of hardware.

IP reuse enables the team to leverage the cost of design and verification across multiple designs and is proven to increase productivity. For design teams to extract the maximum benefit of an IP reuse strategy, however, the onus is on IP providers to supply not only the IP but also the configuration tools to facilitate the easy customization of the IP to the designer's requirements.

At higher levels of abstraction, design and verification can be faster because of a more concise design description. Yet questions remain about the correspondence of higher-level abstraction models to real-world implementations.

The benefit of moving CPUs and memory to software is that software solutions are inherently more flexible, offer field programmability and are low-risk. But there is always a risk that performance may be inadequate for a particular application, and programming multiprocessor designs can be challenging.

A combination of all of these tactics, within a platform-based design methodology that leverages the strengths of each, is one way to take advantage of the greater amount of available silicon. Such an approach provides for IP reuse for nondifferentiated parts of the design; software for nonperformance-critical, application-specific functions; behavioral synthesis for performance-critical, application-specific functions; and traditional hardware engineering where behavioral synthesis is inadequate.

Of the above, IP reuse has the greatest potential for closing the design capability gap. By leveraging existing IP, designers can focus on creating new IP that differentiates their product from others that reuse a similar mix of IP.

Platform-based design is an IP-reuse strategy that offers the chip industry the best chance yet of solving the multitude of productivity and verification problems inherent in creating system-on-chip (SoC) designs. IP is delivered with configuration tools that enable designers to rapidly select the desired options to automatically configure it.

The potential for automation has been difficult to realize, however, because IP documentation and packaging formats vary widely among IP providers. In addition, the techniques for describing IP were not generally machine-interpretable.

Enter XML
Many of these issues are being addressed with the introduction of the Spirit (Structure for Packaging, Integrating and Reusing IP within Tool flows) Consortium's XML schema, which is a specification for providing data that documents the functionality and configurability of intellectual property. This standard IP metadata description in XML code aims to capture all the IP data book and configuration information required to integrate IP into a design. It does so in a machine-interpretable format that facilitates automation of the process. IP users don't have to waste time trying to characterize IP to fit it into their design flows.

There are two key advantages to using XML for the description of component and system designs to document intellectual property:

• XML is an open, extensible data standard controlled and maintained by the World Wide Web Consortium. XML data can be read, exchanged and converted for many different classes of applications.
• Many applications (both EDA and non-EDA), class libraries and development environments already support XML-based tool development in many software languages.

The most obvious platform-based design strategy to have emerged is the delivery of configurable intellectual property along with the tools and XML documentation that enable this configurability within different design environments.

A second emergent design strategy involves tools that configure complete designs. These tools look at the overall design and modify or optimize the design according to design requirements.

These new tools will not only process the existing design data but also update the XML documentation appropriately. These tools make optimum use of new hardware resources in a design, synthesize the hardware with the appropriate bus structures and create the XML description file for the newly created hardware. This enables the automatic integration of the hardware into the existing design.

John Wilson (john_wilson@mentor.com) is product manager for the Platform Express line for Mentor Graphics Corp. (Newbury, England).

See related chart