Low Power System Design Techniques Using FPGAs
EE Times: Latest News Low Power System Design Techniques Using FPGAs | |||
Jason K. Lew (11/01/2004 10:00 AM EST) URL: http://www.eetimes.com/showArticle.jhtml?articleID=51201337 | |||
The advantage of utilizing a combination of low-power components in conjunction with low-power design techniques is more valuable now than ever before. Requirements for lower power consumption continue to increase significantly as components become battery-powered, smaller and require more functionality.
When programmable logic devices are included in low-power applications, it is important to constrain the design for power efficiently. The following sections discuss various methods of reducing dynamic and static power consumption and provide some examples that show how to minimize power consumption. Sources of power consumption Inrush current is device-specific. For example, SRAM-based FPGAs have a high inrush current because on power-up these devices are not configured and need to actively download data from external memory chips to configure their programmable resources, such as routing connections and lookup tables. Conversely, anti-fuse-based FPGAs do not have a high inrush current since they do not require power-on configuration. Much like inrush power, standby power depends heavily on the electrical characteristics of a component. Due to the extensive number of SRAM cells within SRAM FPGA interconnects, they can consume hundreds of milliamps even at standby. Since anti-fuse FPGAs have metal-to-metal interconnects, they do not require the additional transistors, and hence power, to retain interconnects. However, for both FPGA process types, leakage current increases as process geometry shrinks, which exacerbates the power problem.
As an additional dilemma, dynamic power can easily be several times greater than standby power. Dynamic power is proportional to the frequency of charging and discharging of internal parasitic capacitances of a component, such as registers and combinatorial logic, so optimizations are generally design-oriented. Cutting power consumption
Adding latches at the inputs of large combinatorial logic (e.g., wide bus multiplexer) can suppress invalid switching activity, because inputs are latched only when the outputs are supposed to be updated. Similarly, control registers can be implemented to enable or disable lower-level modules (e.g., state machines in submodules). Holding large buses and submodules in a constant state helps reduce the amount of irrelevant switching.
System-level savings
Unfortunately, microprocessors usually need to handle interrupt service routines across multiple devices, which tends to keep the microprocessor out of sleep mode. For that reason, offloading peripheral operations and interrupt control to a low-power FPGA significantly reduces power consumption. A low-power interrupt controller or data coprocessor implemented in an FPGA can handle some of the interrupt activity on its own, and avoid having to wake up the microprocessor for lower-priority transactions. For systems where low power is vital, employing power reduction design techniques with appropriate low-power programmable logic devices helps keep system power consumption to a minimum.
Jason K. Lew (jlew@quicklogic.com) is an applications engineer for QuickLogic Corp. (Sunnyvale, Calif.).
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