Achieving Reuse with both Modifiable IP and Configurable IP (LSI Logic)

One way to increase the chances of achieving high volume for an ASIC design is to make functional differentiations in the design. Such differentiations can often provide a market advantage that can drive larger sales. Unfortunately, differentiating often means designing from scratch, but with multimillion-gate designs and limited engineering resources, designing completely from scratch is rarely feasible.

Third-party IP that can be configured via scripts or synthesis parameters to generate different netlists as "configurable IP" provides some flexibility. But it isn't necessarily differentiating since the same configuration is also available to the ASIC designer's competitors. Another solution to this problem is to create and offer modifiable IP. Often called a reference design, this modifiable IP enables an ASIC designer to easily make differentiating changes to the IP and quickly verify those changes.

Most ASIC designers who have tried to take someone else's code and make changes to it will argue that it's easier to start from scratch than to try to learn, modify and validate unknown code. For much of the IP out there, this is likely to be true. Configurable IP, for example, is probably the most difficult IP to modify because it contains so many ifdefs and parameters that the code is nearly impossible for anyone other than the original designer to understand. Configurable IP relies on putting all the variants of the code in the design and providing mechanisms for selecting the appropriate code with a script or at synthesis or simulation time.

Modifiable IP is completely different. Modifiable code provides only the most common — and hopefully the easiest to understand — configuration in the design. The other configurations are not cluttering up the code. The IP developer only needs to validate one configuration. With configurable IP, all possible combinations of configurations need to be validated. Depending on the number of configurations, this can result in a significantly different cost of development between the two different types of IP. This is part of the reason that configurable IP has only been successful in a few areas with high-value IP like processor cores and memory controllers.

For modifiable IP to have value, both the IP and verification environment must be designed in a modular manner. Great thought must be put into how and where an ASIC designer is going to make changes. The sections that are expected to be modified should be separated from the code that won't be modified. For example, in a processor reference design, most ASIC designers will want to add and remove peripherals from the processor bus, which will require modifications to the memory decoders and bus mux structures. On the other hand, very few customers will want to make changes to the UART. If the processor reference design is structured to accommodate this, ASIC designers can get a huge jump-start on their custom embedded-processor system development.

Modifiable IP can provide customers with the ability to customize and differentiate, without the investment of starting completely from scratch. This is a popular option for cell-based ASICs, which typically have schedules and volumes to justify the modifications.

But if the unit volumes are not quite large enough or time-to-market pressure is too great for cell-based ASICs and modifiable IP, platform ASICs become the alternative. If a platform ASIC approach is chosen, designers should shift their focus to IP that doesn't require modifications. Then there are two other flavors of IP that ASIC designers can turn to: configurable IP and predefined IP.

Both configurable and predefined IP are thoroughly validated in all the possible configurations and often come with a guarantee of some kind. The IP is typically encrypted or obfuscated both to protect the IP and to prevent the ASIC designer from making modifications. The difference between configurable and predefined IP is that the predefined IP doesn't have any synthesis configuration options. Often configurable IP is even used as the source to generate predefined IP.

The ability to configure different functional netlists from a single core isn't really valuable for the ASIC designer; it's valuable to the IP provider. ASIC designers don't need a highly configurable core, because in the end they are going to be forced to choose a specific configuration to put in silicon. Configurable IP is typically created because it allows the IP provider to service a larger number of applications with a single core, giving it better return on investment. The best solution for the designer is to provide a timing-closed hardmac and netlist for the configuration he or she requires. This is the value of predefined IP.

If the IP provider researches the ASIC designer's markets, preselects the optimal configurations and optimizes those configurations for a particular technology, the designer gets much more value than from simply generating a specific configuration from a configurable core. This is often done by the ASIC vendors instead of the third-party IP provider since the company has an intimate understanding of its technology and the markets that it serves.

ARM Ltd. and MIPS Technologies Inc., for example, provide their processors to ASIC vendors as configurable IP with options like changing the cache size or removing the floating-point unit. The ASIC vendor is then able to choose a popular configuration for a specific market, optimize that configuration for a particular library and offer it as a predefined IP. This is common with things like processors, processor systems, protocol cores and memory controllers.

In addition to the benefits of predefining the configuration and optimizing the IP to a particular technology, predefined IP has another clear advantage. If the functionality isn't changing, then it becomes much easier to provide software models like System C or Virtio of that predefined configuration along with complete software support for that configuration. Not only does this help the hardware designers get a jump-start on their system by providing them with a fully validated IP package, but the software developers can also start their development in parallel with the hardware development by using the provided software and software models. A processor system that is delivered as predefined IP, for example, can come with a fully operational operating system and complete board support package. By using this complete package out of the box, and making differentiations in the logic surrounding the preconfigured IP, ASIC designers can eliminate much of the hardware and software design and validation and shave months off their schedules.

Jeff Holm (jholm@lsil.com) is senior marketing manager in the Coreware Technology Group of LSI Logic Corp. (Bloomington, Minn.).

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