Digital Power Control Highlights

Figure 1 Voltage/Current Roadmap

In addition to voltage and current control, the new multiphase controllers were required to satisfy many other specification requirements: VID programming, load line regulation, power sequencing, phase current balance, and monitoring and protection. The PWM function in the multiphase controller is becoming a small part of the controller functionality. This demand for more functionality from the controller and the continuing advance of digital technology has pushed many companies to look at digital multiphase control. The proposed solutions vary from the use of digital processors (DSP), microprocessors, and microcontrollers, to the latest software-programmable mixed-signal IC, the ISL6590 introduced by Intersil.

Benefits of Digital Control

Digital controllers offer many advantages over their analog counterparts: improved system reliability, flexibility, and ease of integration and optimization. Overall, they offer an elegant solution to many requirements in the Vcore power regulation specifications.

A system based on a digital controller requires fewer components, which decreases the mean time before failure (MTBF) of the system. For example, all the components for the feedback loop are eliminated; the select on test and select according to design specification components are also replaced by software programming. A change to the design to meet a new requirement may not require new board layout and more engineering time; the changes could be implemented in software.

The added capability of monitoring protection and prevention will also increase the system reliability. For instance, an engineer can choose to monitor the system temperature to decrease the current limit level, or turn on a fan. This scenario will decrease the stress on the power components and fans that in turn will improve the system reliability and would eliminate over specification of components.

The use of software to change the controller functionality makes a system based on a digital controller very flexible. The digital controller offers the ability to add, eliminate or change any system parameter in order to meet new requirements, or to optimize and calibrate the system. For example, the same voltage regulator model (VRM) can be programmed to meet different processor specifications such as Load Line (LL), voltage identification (VID), and current or voltage requirements, without any hardware changes. Due to the ease of integrating communication capability, the digital controller also facilitates the ability to integrate and cascade multiple systems together. For example, in multi-VRM boards, current sharing could be implemented through a standard communication bus without the need for any hardware additions.

Digital Control IC Implementation

In order to choose the ideal digital controller IC for the application, the power supply engineer will have take into consideration the performance and the capabilities of many digital IC blocks that normally do not exist in an analog controller IC. Three blocks in particular form the heart of a digital controller: an anti-aliasing filter, an analog to digital converter (ADC), and a digital pulse width modulator (DPWM). See Figure 2.

Figure 2 Major Digital Controller Blocks

a)Anti-Aliasing Filter
The Sampling Theorem indicates that a continuous signal can be properly sampled, only if it does not contain frequency components above one-half of the sampling rate. So, if the sampling rate is 2MHz, then an anti-aliasing filter with "20dB gain at 1MHz would be practically expected. The importance of the anti-aliasing filter arises from its effect on the total system bandwidth. For example, assume that we only can have an RC type of low pass filter, with transfer function of the form:

To have -20dB gain at 1MHz, half the sampling frequency of 2MHz, the pole of H_Alias has to be at 100kHz, which will introduce a phase lag of 45° at 100kHz. If a power stage is switching at 1MHz, an analog control loop with a crossover frequency of 200kHz can easily be obtained. With this digital implementation, the crossover frequency will be limited to below 100kHz if we do not allow any phase lag to be introduced in the feedback loop by the anti-aliasing filter. To solve this problem we could use an active filter with more poles, or increase the sampling frequency.

b) A/D Converter
The A/D Converter block consists of two main sub-circuits: the sample and hold and the ADC itself. The sample and hold block adds a delay in the loop according to that can be approximated as:

: where TADC is the A/D Converter sampling period.

In order to decrease the delay, i.e. decrease the phase lag, the sampling period TADC of the A/D Converter needs to be increased.

A wide choice of ADC architectures exist that differs in resolution, bandwidth, accuracy, and power requirements. The major ADC architectures are flash (all decisions made simultaneously), successive approximation (where a successive approximation shift register is the key defining element), and pipelined with multiple flash stages. Each has it own unique set of pros and cons.

The Flash Architecture: Sets of 2n-1 comparators are used to directly measure an analog signal to a resolution of n bits. The flash architecture has the advantage of being very fast because the conversion occurs in a single cycle. The disadvantage is that it requires a large number of comparators; the number of comparators needed for an n-bit ADC is equal to 2n-1. For instance, a 10-bit A/D converter needs 1023 comparators, which makes it hardware intensive even for an integrated controller.

The Successive Approximations Architecture: This approach uses a single comparator over many cycles to make its conversion. The successive approximation (SAR) converter only needs a single comparator to realize a high resolution ADC, but it requires n comparison cycles to achieve n-bit resolution. SAR has a major disadvantage since it takes too many cycles to convert the analog signal, which will introduce a large phase lag in the feedback loop. For example, a 10-bit conversion will introduce 10TADC delay.

The Pipelined architecture with Multiple Flash: This is the middle ground between the fast flash converter and the high resolution SAR. A pipelined converter divides the conversion task into p consecutive stages. Each of these stages consists of a sample and hold circuit, an n-bit flash converter, and an n-bit D/A converter (DAC). A pipelined converter with p-pipelined stages, each with an n-bit flash converter, can produce a high-speed ADC with a resolution of k = p x n bits using (2ⁿ - 1) comparators. For example, a 10-bit, two stage pipelined converter would require 62 comparators as compared to 1023 for the flash, and will take only two cycles for the conversion compared to 10TADC on a SAR.

From the discussion regarding the anti-aliasing filter and the delay introduced by the Pipelined or the SAR A/D converter, we see clearly the need for high sampling rate. The number of bits needed can be based on the resolution of the measurement required. In order to satisfy a specified output voltage regulation δVout, the ADC resolution has to have an error less than the allowed variation of the output voltage.

If the maximum output regulation is δVout, the maximum voltage of the ADC is VADCmax and the output voltage Vout is scaled by a gain G to meet the ADC voltage levels, then the least significant bit of the ADC has to be less than the product of the maximum ripple and the Gain.

where k is ADC number of bits

Solving for k we get:

For example, if the output voltage ripple δVout is 5mV, the output is 2V, and the maximum ADC input voltage is 1V, a scaling of G = 0.5 will be required before the input to the ADC. At a minimum, an ADC with kADC = 10 bits is required in this case.

c) Digital Pulse Width Modulator
An analog controller has no inherent limit on the possible pulse width generated. On the other hand, a DPWM produces a discrete and finite set of PWM widths. From the output point of view in steady state, only a set of discrete output voltages is possible. Because DPWM is part of the feedback loop, it is necessary that the resolution of the DPWM be high enough so that the output will not display what is known as a limit cycle. In a limit cycle the output goes into an oscillation of fixed amplitude and frequency, irrespective of the initial state.

The minimum number of bits needed so as not to display any limit cycle depends on the topology, the output voltage, and the ADC resolution. For example, in the buck converter:

Vout = DVin where D is the Duty Cycle.

If we differentiate the above equation, we get:

ΔVout = VinΔD

Replacing Vin by Vout/D , we get ΔD = DΔVout/Vout.

Therefore, if we have kpwm bits in our PWM modulator, the least significant bit is:

From the preceding paragraph, the minimum output ripple is:

Using the result from above we get:

Where kADC is the ADC number of bits.

As was shown in the previous example, if δVout = 5mV, the output is 2V, the maximum ADC input voltage is 1V, and a scaling of G = 0.5, then a minimum of 10 bit ADC is required. With kADC = 10 bits and assuming a minimum duty cycle of 0.1 (D = 1), a minimum of 14 bits is required for the Digital PWM.

Over the years, power supply designers have gained a strong knowledge of how to choose an analog power supply controller in order to meet the required specifications. With the introduction of digital controllers, the choices are not as clear. The digital controller requires the designer to pay attention to more complex IC blocks. In order to achieve the digital controller advantages of improved system reliability, flexibility, and ease of integration and optimization, the power supply designer must select the correct ICs for the application. The anti-aliasing filter, analog to digital converter (ADC), and the digital pulse width modulator (DPWM) are the heart of the digital controller IC. Special design considerations of these blocks are key to achieving superior overall system performance.