D&R Industry Articles (October 2003)

Articles for the Week of October 27, 2003

• Commentary: Fast ASICs with structure (by Clive Maxfield)
• Subsystem design key to wireless gaming
• Understanding the MAC impact of 802.11e: Part 1 (By Simon Chung and Kamila Piechota, Silicon and Software Systems)
• Understanding the MAC impact of 802.11e: Part 2 (By Simon Chung and Kamila Piechota, Silicon and Software Systems)
• Developing and Integrating FPGA Co-processors with the TiC6X Family of DSP Processors

Articles for the Week of October 20, 2003

• Structured ASICs allow improved design flow
• SoCs challenge production test methods
• Serial storage SoCs demanding to test
• Scan-based transition-fault test can do job
• Open architecture ATE tackles test woes
• Vectorless test: best bet for high-speed I/O
• Traveling at the speed of memory
• Source-synchronous clocks pose challenges
• Architecture-based vs. flow-based approach to DFT
• Scalable Verification Environment Using OCP Compliant Cores and eRM Compliant eVCs
• Design Security in Nonvolatile Flash and Antifuse FPGAs
• Understanding the Semiconductor Intellectual Property (SIP) Business Process
• Attacking the Verification Challenge: Applying Next Generation Verification IP to PCI Express-based Design (by N. Mullinger, J. Hopkins & R. Hill from Synopsys)
• ASICs demand test perspective
• SoC creation requires rules

Articles for the Week of October 13, 2003

• Why platform-based design works better than a discrete IP approach (by David Fritz, ARC International)
• Network DRAMs Shine in Datapath Designs
• Design of Base I/O Libraries (by Ron Nikel, Co-Founder and CTO of TriCN)
• Rapidly Implementing Synthesizable ARM IP (By Alan Gibbons, Synopsys and John Biggs, ARM)

Articles for the Week of October 6, 2003

• Under the Hood of Library IP (by Brani Buric and Mike Colwell, Virage Logic)
• Lifelong testing prescribed for complex chips

Articles for the Week of September 29, 2003

• Commentary: Synopsys memory IP users seek RTL source code
• Programmable logic carves further into the ASIC's territory
• The future of programmable logic