D&R Industry Articles (July 2005)

Articles for the Week of July 25, 2005

• Selecting PCI Express IP for Your Design
• Back to the basics: Programmable Systems on a Chip
• Replacing flash memory for embedded applications
• Expand your 8051 memory
• ESL enables software-driven SoCs
• Networks on Chip - Challenges and Solutions
• SOI eases radiation-hardened ASIC designs
• How Verilog-AMS accelerates transistor modeling

Articles for the Week of July 18, 2005

• Integrating Linear Power Regulation On-Chip
• Getting the most from multiprocessor SoC design
• A Real-Time Image Processing with a Compact FPGA-Based Architecture
• Using SystemVerilog Assertions in RTL Code

Articles for the Week of July 11, 2005

• Automated Transistor-Level Optimization in Standard-Cell Based Digital Design
• NOR continues to battle NAND flash memory in the handset
• Simultaneous Exploration of Power, Physical Design and Architectural Performance Dimensions of the SoC Design Space using SEAS
• Using a "DSP-free" design for VOIP-enabled end-points
• Improving yield in RTL-to-GDSII flows

Articles for the Week of July 4, 2005

• Efficient Verification of CAN based System
• AICP: AURA Intelligent Co-processor for Binary Neural Networks
• Micro-threaded Row and Column Operations in a DRAM Core