D&R Industry Articles (December 2006)
Articles for the Week of December 18, 2006
Fully Digital Implemented Delta-Sigma Analog to Digital Converter
This paper shows an approach which only uses 2 resistors and 1 capacitor which are located outside a pure digital chip. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the ADC also can be used for FPGAs.- Practical Applications of Statistical Static Timing Analysis
- Five things to keep in mind when selecting an embedded mobile/consumer SoC
- SPI-S--a next-generation interface for serial physical interconnects
Articles for the Week of December 11, 2006
A Platform-Based Technology for Fault-Robust SoC Design
When designing a System-On-Chip (SoC) for safetycritical or high-reliability applications, the design space that a system architect must consider is rather large due to the variety of faults that can affect the SoC, the different failures that these faults can generate and the wide set of techniques that can be used to detect, confine or stop the resulting hazards, each one with its efficiency and cost.- PoP, SiP, MCM, MCP or SoC? Assessing the mobile/embedded design tradeoffs
- PSL Verification Package for the Open Core Protocol
- Tutorial: Floating-point arithmetic on FPGAs
- FPGA-to-ASIC integration provides flexibility in automotive microcontrollers
Articles for the Week of December 4, 2006
How NXP uses Spirit/ESL-based IP ''Yellow Pages'' to speed System-on-Chip design time
You can either spend a month hand-crafting the last few hundred square microns of silicon out of a system-on-chip (SoC) design or you can put your product on the market one month quicker.- How to implement high-speed 667 Mbps DDR2 interfaces with FPGAs
- Codec from Canada, CRC-WVC, outperforms H.264 video with wavelets
- How to use CPLDs to implement a QWERTY keypad
- ''Enterprise'' System Level (ESL) Verification -- PART II