D&R Industry Articles (March 2007)

Featured Article

Practical Applications of Data Abstraction Techniques for Embedded Systems Debug

This paper will present in detail practical applications that illustrate the host of issues that hamper the debug of an embedded platform as well as methods to mitigate these problems. We will discuss the debug of a ''Network on Chip'' (NoC) communication mechanism, which while providing potential performance, power and interconnect flexibility gains for the target system, disguises implementation detail to a great degree.

Featured Article

Hardware Implementation of a Combined Interleaver and DeInterleaver

The implementation of any Wireless Base band system as an IP is complex. One of the key components in the IP is the Interleave / DeInterleave process, which requires a careful implementation to obtain an optimal solution in terms of area and speed. The Interleave / DeInterleave process can consist of multiple stages and the approach of implementing these stages individually is not optimal.

Featured Article

An Overview of Secret Key and Identity Management for System-on-Chip Architects

The paper begins with a brief overview of techniques for identification and authentication then follows that with a discussion of technical means to implement them in a System-on-Chip (SoC).

Featured Article

Making your UWB solutions ''Future Proof''

New technologies bring with them new opportunities as well as new uncertainties. In order to make best use of technology, one has to be prepared for today as well as for the future. This often involves tradeoffs between current opportunities and future potential. In this article, the effort is to illustrate a possible tradeoff one has to make while developing the solutions based on Ultra Wideband.

Featured Article

Complex SoC Verification using ARM Processor

A verification environment with a mix of C tests for debugging (for embedded processor) and verilog test bench for monitors and automated checkers is used for successfully verification of an ARM based SoC design. This paper provides more detailed illustration that combines C (embedded test cases) and Verilog test bench for system level verification and also introduces verification techniques that helps in reducing verification time of SoC's .