D&R Industry Articles (May 2007)

Featured Article

RAID6 accelerator in a PowerPC IOP SOC

This paper describes a PowerPC system-on-a-chip (SOC) which is intended to address the high-performance RAID market segment. The SOC uses IBM's Core-Connect technology to integrate a rich set of features including a DDRII-800 SDRAM controller, three 2.5Gb/s PCI-Express interfaces, hardware accelerated XOR for RAID 5 and RAID 6, I2O messaging, three DMA controllers, a 1Gb Ethernet port, a parallel peripheral Bus, three UARTs, general purpose IO, general purpose timers, and two IIC buses.

Featured Article

Realizing the Performance Potential of a PCI-Express IP

This paper describes challenges involved in realizing the maximum performance of a configurable interconnect IP (GPEX - Rambus PCI Express Digital Controller). The following sections describe how various performance metrics such as roundtrip latency and bandwidth can be used to characterize a PCI Express IP performance and its impact on the system. The ideas presented can also be applied to other high speed interconnect architectures like RapidIO and Hypertransport

Featured Article

e Verification Environment for FlexRay Advanced Automotive Networks

FlexRay is the vehicle networking standard being backed by all major automotive manufacturers because it is fast and flexible while being reliable and deterministic. NXP (formerly Philips) Semiconductor is a founding member of the FlexRay Consortium and has invested heavily in a comprehensive e verification environment for FlexRay, which IPextreme is taking to market.

Featured Article

Reusable debug infrastructure in multi core SoC : Embedded WiFi case study

This paper outlines a system level reusable hardware-software debug infrastructure for a complex multi core SoC and describes how this can be integrated with existing third party debug tools such as ARM MultiIce and logic analyzers. The concepts are illustrated through the case study of multi core multi million gate embedded WiFi project.