D&R Industry Articles (July 2007)

Featured Article

A New Methodology for Hardware Software Co-verification

Traditional methods of hardware software co-verification use either the industry standard accelerators/emulators or the instruction set simulators. Both the methodologies are well proven and are well established in SOC verification environment. The design, development and validation of device drivers require these tools and software and it would be an expensive proposition for IP developers.

Featured Article

Transaction Level Model of the USB On-The-Go controller IP core

The paper describes a transaction level model of the serial bus controller compliant to USB On-The-Go specification [1]. The model has been developed as an abstraction of an existing IP core, written in VHDL. The possible use in the development or testing of a software driver was addressed too.

Featured Article

Measurable Verification Methodology for Highly Configurable IP Cores

This paper describes the methodology based on use of functional coverage technology for measurement of quality of IP. In this methodology, the regressions are run on RTL generated by selecting hard configuration parameters randomly. Constraints are defined such that illegal combinations of such parameters are avoided. Functional coverage is used for both soft configurable options (control registers) as well as hard configurable options (ifdef parameters).

Featured Article

SoC interconnect performance verification methodology based on hardware emulator

This paper describes an interconnect performance verification methodology which was developed for a complex multi source digital television SoC project. The historical and technical reasons of the interconnect performance verification are detailed in the introduction. Then the verification platform, the hardware measurement agent (called spy), the methodology flow and the measurement method are described. The emulator resource optimization is discussed. This methodology was extended for CPU real time constraints verification.

Featured Article

Development of Verification Environment for Layered Protocol using SystemVerilog

This paper explains how individual layered specific verification components such as, Transactor, Checker, Monitor which can be developed using SystemVerilog can be reused when you have all the layers connected at the sub-system and system level, and hence maximizes the verification productivity gains.