D&R Industry Articles (September 2007)
Articles for the Week of September 24, 2007
MpNoC Design: Modeling and Simulation
We present in this paper a model and an implementation of a communication network called mpNoC. This IP permits non-regular communications between PEs in an efficient way. MpNoC is integrated in the mppSoC platform.- Demystifying multithreading and multi-core
- How to turn every FPGA LVDS pair into a complete SERDES solution
- Using model-based design to test auto embedded software
Articles for the Week of September 17, 2007
Design of a C library for the implementation of 3D graphics applications on a SoC
In this paper a new approach to the implementation of 3D graphics applications on a SoC architecture is described. This approach is meant to be particularly flexible, in order to be used in different kinds of systems: it is based on the realization of software libraries, that are developed using the C programming language.- Employ dynamic power reduction in an ASIC
- Cost-effective two-dimensional rank-order filters on FPGAs
- Multi-Core Processors: Driving the Evolution of Automotive Electronics Architectures
- A New Approach to In-System Silicon Validation and Debug
Articles for the Week of September 10, 2007
A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect
This paper describes the development of a Multiprocessor System-on-Chip (MPSoC) with a novel interconnect architecture and an enhanced compiler support for programmability.- How to use FPGAs for quadrature encoder-based motor control applications
- DDR2 Signal Integrity
- Overcoming Latency in PCIe Systems
- Hardware emulator debugs Linux driver
- H.264 "zero" latency video encoding and decoding for time-critical applications
Articles for the Week of September 3, 2007
A Unified Analog Design and Process Framework for Efficient Modeling and Synthesis
A fundamental characteristic of analog/RF technology development is the sensitivity of analog components/MEMS/circuits to the various manufacturability/performance trade offs that must be made. The iterative loop between designers and technologists during technology definition is critical for timely product development which is difficult to realize in practice! This problem is becoming a major stake especially at nanometer scale.- Top-down DSP design for FPGAs
- Polyphase Video Scaling in FPGAs
- Introduction to and Regression Test for OCP SystemC Channel Models
- FPGA design from scratch