D&R Industry Articles (April 2008)

Articles for the Week of April 28, 2008

Featured Article

System Packet Interface (SPI) 4.2 IP Core

The paper describes the architecture of a novel performance-enhanced SPI 4.2 IP Core. It also mentions, through examples and performance statistics, the improvement in the performance of SPI 4.2 data transfer as against the sub-optimal IP cores available.

• Virtual prototyping boosts model-driven Design for Six Sigma methodology: Part 3 of 3 - Design example: Electronic throttle control
• Serial ATA and the evolution in data storage technology

Articles for the Week of April 21, 2008

Featured Article

SystemC Mixed-HDL IP Reuse Methodology

This paper proposes a methodology which addresses the clear needs of the ever-growing SystemC mixedlanguage designs by delivering critical capabilities, including advanced verification features such as; SystemVerilog Assertions (SVA), cover-groups, SystemC Verification (SCV), and more.

• Development and use of an Instruction Set Simulator of 68000-compatible processor core
• C-based coprocessor design, part 2: Datapath customization
• What floorplan information is needed for synthesis
• Overcome power, size and cost when developing optimized '4G' chipsets for handhelds
• A Power Integrity Wall follows the Power Wall!
• FPGA-based flexible Ethernet switch reduces development time

Articles for the Week of April 14, 2008

Featured Article

Verification of IP Core Based SoC's

In an IP-Core based SoC design. A streamlined verification and analysis flow can contribute significantly to the success of a product. A strategy is devised for a more streamlined approach in IP-core based SoC verification which helps in smooth transition from design to chip tape-out stage.

• FPGA based Complex System Designs: Methodology and Techniques
• C-based coprocessor design, part 1: SIMD architecture
• Software-defined silicon: Why can't hardware be more like software?
• DDR3 memory - How to Win with Low Power and Reduced Thermal Solutions

Articles for the Week of April 7, 2008

Featured Article

Accurate System Level Power Estimation through Fast Gate-Level Power Characterization

• Interfacing High Performance 32-bit Cores To MCU-based Memory Architectures
• Mobile video: ARM vs. DSP vs. hardware
• Reducing Power in Embedded Systems by Adding Hardware Accelerators
• Virtual prototyping boosts model-driven Design for Six Sigma methodology: Part 1 of 3 - The challenges and tools
• Preservation of Circuit Structure and Timing during Fault Emulation in FPGA
• How to implement a high-definition video design framework for FPGAs
• Viewpoint: Verification flow should be front and center
• Designing a mobile handset? I2C bus protocol offers cost savings

Articles for the Week of March 31, 2008

• Verification IP Reuse For Complex Networking Asics
• Open Verification Methodology: Why Now?
• Consolidating the MCU market around the ARM architecture