D&R Industry Articles (May 2008)

Articles for the Week of May 26, 2008

Featured Article

Re-Use of Verification Environment for Verification of Memory Controller

With the complexity of the design on the rise, coverage of functional verification is one of the increasing challenges faced by the design and the verification teams. Reducing the verification time without compromising the quality of the verification is the greatest challenge to the verification engineers.

• NV memory beyond floating gateNV memory innovators
• How to perform meaningful benchmarks on FPGAs from different vendors
• ESL Methods for Optimizing a Multi-media Phone Chip
• Tips on using CPLDs to reduce system processor power consumption
• Design Challenges Drive Need for New Routing Architecture

Articles for the Week of May 19, 2008

Featured Article

Rapid Creation of Application Models from Bandwidth Aware Core Graphs

We present a methodology that allows the rapid creation of application models from bandwidth aware core graphs that are available in the literature for a wide range of applications and we discuss their applicability to the rapid exploration of multiple Networks on Chip (NoCs) layout organizations.

• An MDE Approach For Implementing Partial Dynamic Reconfiguration In FPGAs
• Multimode: How to design a programmable baseband device for multiple wireless standards
• How to design portable handsets using CPLDs
• Debugging a Shared Memory Problem in a multi-core design with virtual hardware
• Static Checks for Power Management at RTL
• Preserving The Intent Of Timing Constraints
• Massively parallel processing arrays (MPPAs) for embedded HD video and imaging (Part 1)

Articles for the Week of May 12, 2008

Featured Article

Case Study: Annotating OVL 2.0 with SVA Assertions

In this case study we attempt to annotate a subset of OVL 2.0 checkers using equivalent SVA properties. In doing so, we define the equivalence between checkers, or assertions, based on what input sequences they can detect as failure sequences

• Configurable SoC Platform for Bluetooth Applications
• Characterizing Nanometer CMOS PLLs, Sigma-Delta ADCs and AGCs
• How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 2
• Only secure hardware can safeguard standards
• Insuring silicon Intellectual Property interoperability with OCP consensus profiles
• 20th Anniversary article: Full simulations with partial hardware
• H.264 encoder design using Application Engine Synthesis

Articles for the Week of May 5, 2008

Featured Article

An Efficient Software-Hardware Partitioning for Transport Demultiplexer

In this paper, we present an efficient software-hardware partitioning for transport demultiplexer. We develop transport demultiplexer software model and simulate it on reduced instruction set computer (RISC).

• DSP or FPGA? How to choose the right device
• Designing Around an Encrypted Netlist: Is The Pain Worth the Gain?
• An architecture for designing reusable embedded systems software, Part 2
• Asynchronous DSPs: Low power, high performance

Articles for the Week of April 28, 2008

• IP Core of On-line ICA Algorithm
• How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 1
• The Relevance of System Design
• An architecture for designing reusable embedded systems software, Part 1