D&R Industry Articles (November 2008)
Articles for the Week of November 24, 2008
Build low power video SoCs with programmable multi-core video processor IP
With power consumption comparable to ASICs, this SoC architecture scales to 1080p and beyond.- Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 1
- Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 2
- Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 3
- Unified Verification for Hardware and Embedded Software Developers
Articles for the Week of November 17, 2008
Additional Articles- Squeeze power efficiency out of processor-based designs -- Part one
- Solving FPGA I/O pin assignment challenges
- Planning, adopting and implementing adaptive reuse
Articles for the Week of November 10, 2008
Got OCP? The Role of the OCP in Multicore Designs
A brief exposition on the role of the open core protocol (OCP) in system-on-chip designs and the impact of the newest Version 3.0 on the design of multiprocessor SoCs.- Built-In DMA Engines Unleash Power of PCI Express Switches
- Follow guidelines to develop an efficient portable power solution
- Automotive radio receiver harnesses Software Defined Radio
- Video-image processing with customizable DSP-FPGA platform
Articles for the Week of November 3, 2008
A SystemC/TLM based methodology for IP development and FPGA prototyping
With the advent of System-on-Chip technology, designs are becoming bigger in size and thus highly complex, time-to-market is becoming critical, and at the same time, RTL methodologies are generally becoming insufficient to fit into this new role. These factors are driving designers to explore new methodologies for early verification of complex IPs (HW as well as SW) as well as complete system.- Changing hardware requires more aggressive testing
- Open source in consumer electronics: What, why and how
- Programmable logic use in handsets--The basics