D&R Industry Articles (July 2009)

Featured Article

SystemVerilog-VHDL-SystemC Verification IP Reuse Methodology

This paper proposes a methodology that makes use of the SystemVerilog bind construct to achieve this. The proposed methodology will help verification engineers unleash the full potential of their VIP by not only allowing it to be comprised of elements written in different languages, but also allowing it to be reused in a mixed-language environment to verify design IPs written in different languages.

Featured Article

Requirements for Intellectual Properties in Safety Critical Airborne Electronic Hardware

This paper will explain some issues related to Intellectual Properties (IP) which are part of complex components (ASIC, PLD, FPGA, microprocessors) in the domain of airborne electronic hardware.

Featured Article

Small but Deadly - the Life Cycle of an I/O Bug

Some years ago, Duolog worked with a customer to develop a verification infrastructure for system-level validation of a large multimedia chip. Duolog developed a modular, programmable chip-level testbench, incorporating peripherals, memories, reset, clocks and control. While the delivery of the testbench went well there were some interesting dynamics as the Duolog team as well as software, integration, validation, DFT and IP teams were drawn into an I/O layer heavily infected with I/O bugs that were small, but deadly.

Featured Article

Modelling OCP Interfaces in SystemC: Standards built on top of OSCI's TLM-2

This paper describes the approach adopted by OCP-IP to providing SystemC modelling interfaces for a real memory-mapped bus family. TLM-2.0 has shown itself to be an effective and efficient base technology for all variants of OCP at all levels of abstraction, from cycleaccurate to untimed.