D&R Industry Articles (September 2009)

Featured Article

Transactions in an OVM SystemVerilog Verification Environment

Modeling a verification environment with transactions encompasses many areas, including test bench design and debug, golden model comparison, functional verification between abstraction levels and overall system operation. This paper will discuss certain techniques for modeling with transactions in each of these different abstraction levels and how to effectively combine them using the OVM and SystemVerilog.

Featured Article

A 24 Processors System on Chip FPGA Design with Network on Chip

In this paper we present a single FPGA chip implementation of a NOC based shared memory multiprocessor system with 24 processors connected to a main memory composed of 4 DDR2 banks. All the processors and DDR2 memories are connected to a NOC through Open Core Protocol (OCP-IP) interface. The MPSOC have been validated and evaluated through actual execution with matrix multiplication application. A Global Asynchronous Local Synchronous (GALS) design methodology have been adopted throughout the design cycle and exploited for clock trees designs.

Featured Article

Semiconductor IP Quality - A User guide

This paper provides a holistic approach for to how to ensure your customer’s product is going to fulfill its destiny. The key for the IP companies' success is their ability to ensure smooth integration of the IP, and the customer ability to see revenue generated from that product.

Featured Article

Platform Based Design using a design meta-database

In this paper we introduce a method for platform-based design and integration of a System on Chip (SoC) using a centralized design meta-database from which all related design data such as EDA tool command scripts, Hardware Description Language (HDL) files, design constraints and user- documentation can be generated. In this meta-data centric approach we aim to keep the required tool chain complexity and the minimum required meta-data for an IP as low as possible.