D&R Industry Articles (March 2010)

Featured Article

Source Code Analysis in an Agile World

This paper will demonstrate that several of the core principles of Agile cannot be fully realized without implementing a repeatable process for ensuring code that is as bug-free as possible

Featured Article

A Step By Step Methodical Approach for Efficient Mixed-Language IP Integration

This paper looks at mixed-language design integration from both the EDA tool developers’ and designers’ perspectives. It describes different approaches and provides useful insights to help users select the best option for integrating two IP blocks in a mixed-language environment. We will provide practical examples based on real designs

Featured Article

A Flexible, Field-programmable ROM Replacement

For large amounts of on-chip code and data, mask read-only memory (ROM) provides an inexpensive and easily programmed storage mechanism. However, the inability to configure ROM after wafer processing means that information stored in the ROM cannot be changed in the field. Antifuse one-time programmable (OTP) provides a flexible, field-programmable alternative to ROM. An antifuse-based bit cell uses controlled, irreversible thin (gate) oxide breakdown to program a bit.

Featured Article

Initial Investigations into UML Based Architectural Reference Patterns for Set-Top Boxes

This paper analyses a leading-edge Set-top Box (STB) design for architecture reference patterns. Specifically, the following contributions are made: (i) identifying and documenting (in UML) STB architectural reference patterns, and (ii) providing empirical (quantitative) analysis of pattern use.

Featured Article

Embedded Symmetric MultiProcessing system on a SoC with 1.6GHz PowerPC IP in 45nm

Because the dimensions of lithography are now closer to the fundamental physical limits, scaling is more and more difficult and thus multi-core processor solutions are just starting to be more popular in the embedded area. This paper describes in details the features that allow SoCs to be built with up to eight 1.6 GHz PowerPC CPU cores in an embedded system supporting Symmetric Multiprocessing (SMP) architecture. The balancing between CPU execution speed, memory bandwidth and latency, and coherency overhead has been the objective of the design of the PLB6 and the L2 Cache IP's, to reduce as much as possible the drop-off in performance-per-core inherent in an SMP approach.