D&R Industry Articles (November 2010)

Featured Article

A Memory Subsystem Model for Evaluating Network-on-Chip Performance

This paper provides a set of necessary parameters that can be used to generate a highly abstracted DRAM controller and memory. The objective is to keep the abstraction level high enough to make development easy, and at the same time, capture the critical parameters that significantly influence the performance of the system.

Featured Article

A Methodology for Describing Analog/Mixed-Signal Blocks as IP

The development of analog IP blocks shows its own difficulties in that it is still unclear, today, what characteristics those blocks must actually have and how they should be approached. Particularly, there is no broad, openly available stardard for analog IP. This work attempts to help solve this lack of standardisation by presenting a methodology for describing analog integrated circuits (or analog portions of more complex designs) as intellectual property blocks.

Featured Article

Innovation led Business Models for IP's in Product Engineering

Innovation involves two essentially different activities – coming up with a new idea and creating a market out of it. There is no need for the same organization to do both.

Featured Article

Metric Driven Validation, Verification and Test of Embedded Software

Today’s complexity of embedded systems is steadily increasing. The growing number of components in a system and the increased communication and synchronization of all components requires reliable verification, validation and testing of each component as well as the system as a whole. Considering today’s cost sensitivity it is important to find errors as early as possible and to increase the degree of test automation to avoid quality losses because of the increased cost pressure.

Featured Article

eFPGA Creator GUI Tools Suite: A complete hardware and software infrastructure for creating customizable eFPGA IP blocks of Menta

This paper presents a brief overview of new generation of Graphical tools suites we are developing to help our clients quickly and very easily obtain the customized eFPGA IP of their needs (Area, Power, Speed, I/Os, Target node etc.) this phenomenal benefit is hard to achieve with classical device based FPGAs.