D&R Industry Articles (April 2012)

Featured Article

A Digital Design Flow for Differential ECL High Speed Applications

This paper presents a digital design flow in order to design high performance differential Emitter Coupled Logic (ECL) circuits efficiently. The proposed flow is similar to the ordinary digital CMOS Design Flow. It uses standard design tools for gate-level synthesis and layout generation. The differential logic synthesis is separated in two phases. Starting from a synthesized, single-ended HDL design description, a fully differential ECL netlist is generated using a Verilog netlist converter before the layout phase. This results in a short development time and fast verification possibilities. Furthermore, the layout generation can be done in one shot together with digital CMOS components.

Featured Article

The Challenge of the Clock Domain Crossing verification in DO-254

In order to meet high-performance and low-power requirements, FPGA and ASIC designs often include many separate clock domains. This practice creates Clock Domain Crossing (CDC), which occurs whenever a signal is transferred from a clock domain to another. However, these signals may cause data corruption issues, only occurring during post-layout verification, because conventional RTL verification techniques cannot detect resynchronization problems. As a consequence, critical bugs may escape the verification process and simulation does not accurately predict asynchronous silicon behavior.

Featured Article

Enabling High Performance SoCs Through Multi-Die Re-use

This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.

Featured Article

Which USB is right for your application? (Part 3)

In 2007, I wrote a two-part series titled “Which USB is Right for your Application” for Planet Analog (Part 1 and Part 2). Since then, several new and different “versions” of USB have been released. In this article, I discuss how they have been deployed in the market in the almost five years since.

Featured Article

Encoding H.264 without External DRAM : Power and Quality Comparison

This article compares the power consumption and quality of the generated bitstream between two Ocean Logic H.264 encoder cores : OL_H264E that uses external DRAM to store the reference frame store and OL_H264E_CFS that uses a Compressed Frame Store (CFS) technology that does not need external DRAM.