D&R Industry Articles (June 2013)

Featured Article

Latch-up Improvement For Tap Less Library Through Modified Decoupling Capacitors Cells

This article refers to a feature size reduction topology and resulting degradation in latch-up performance. The article proposes a layout for decoupling capacitors so as to improve the latch-up performance of the SoC.

Featured Article

Low Power Design for Testability

Design for testability (DFT) and low power issues are very much related with each other. In this paper power reduction methodologies are discussed for a given design. Power management circuitries are developed to reduce functional power of the design. Power aware Scan Chains are implemented to create test environment which result into reduction in test power. Design for testability is applied to test power management circuits using Power Test Access Mechanism. Also few methods are discussed to implement DFT to test power management circuitry and improve test and fault coverage during ATPG.

Featured Article

A novel approach to ensure complete coverage for validation of communication protocols by inducing jitter and glitches in clock and data

This paper talks about the various challenges in validation of communication protocols. It then proposes a novel approach to ensure complete coverage thus delivering a robust IP.

Featured Article

A need for static and dynamic Low Power Verification

With increasing complexities in power architecture and complex power domain partitioning, it is becoming imperative to drive functional and physical verification of these complex power logic hand in hand. However, despite relentless efforts of verification engineers, some issues may still skip through and make their way to silicon. To ensure that design is compliant with respect to low power constraints defined in CPF, both static and dynamic checks need to be performed using the common CPF. At first, it seems either static verification or dynamic verification alone should be sufficient to catch all the low power related issues and there is no need to run both the checks. But in reality, this is not the case. In this paper, we will discuss the need of carrying both static and dynamic low power checks using a common CPF