D&R Industry Articles (November 2013)

Featured Article

Development of a 4K 10-Bits HEVC Encoder

The new High Efficiency Video Coding (HEVC) video compression standard results from the work of the latest joint project of the ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) standardization groups, performed under the name of the Joint Collaborative Team on Video Coding (JCT-VC) (ITU-T and ISO/IEC).

Featured Article

An Introduction to Caskeid - Wireless Stream Synchronisation IP

It’s a trend happening everywhere today: devices are going wireless and connecting to the Internet. And not just the ubiquitous smartphones, tablets and the smart TV either; add to this a growing list of consumer electronics products: refrigerators, ovens, games consoles, central heating systems, weather stations, radios and home stereo systems. Indeed the simple home stereo is struggling in the digital world. Countless inputs and control methods, incompatible interfaces, and way too many wires have created a home entertainment headache.

Featured Article

Display Driver with on-chip frame buffer and a scalable image compression engine

A display Driver with on-chip frame buffer and a scalable image compression codec reaching visually lossless image quality is presented. The frame buffer compression codec can encode and decode up to eight pixels in one clock cycle. Integrating a whole frame buffer with RGB=888 or 10-10-10 bits into the display driver sharply reduces power dissipated between the AP chip and Display board. The existing working chips are manufactured by both UMC and TSMC 55nm high voltage CMOS process.

Featured Article

How to specify and integrate successfully a measurement analog front-end including its power computation engine in an energy metering IC

Based on the system specification of a typical smart meter, this article demonstrates the importance of carefully selecting the power metering IP solution so that its specification matches the standard requirements and copes with the application challenges. This article then pinpoints thoroughly the various issues that must be taken into account for the selection of the Silicon IP and helps identify the possible trade-offs between the performance of the Mixed-signal Front-end (MFE) and that of the Power and energy Computation Engine (PCE).