D&R Industry Articles (April 2014)

Featured Article

Behavioral Model of a DDR Memory Controller in a DFi - Frequency Ratio System

The paper details the DDR MC Phase encoding algorithm in a DFi™ frequency ratio system. It is intended for a technical audience interested in learning about how the DDR MC encodes the PHY timing information in the Phase- Specific bus. Please refer to the DFi™ 3.1 specification for complete details on frequency ratio systems.

Featured Article

IP Exchange Through Handoff for Easy System-On-Chip Design

This paper provides insight into a novel solution used to build SoCs targeting increased productivity in a complex environment. It describes the IP exchange and checking infrastructure deployed in a live design environment to ensure a well-timed and transparent transference of the sub-systems from the handoff to the implementation team.

Featured Article

SV Assertion Based Error Signaling Checks And Application across popular bus protocols

Today, many External Bus Interface Protocols have error signaling incorporated. The noise and other system anomalies prevent any standard protocol to deliver error-free data. Interconnect protocols without error signaling suffers a performance hit in this regard. Error Signaling minimizes the data loss during a bus transaction. This paper presents an effective approach to verify the compliance of the error signaling implementation with the specification.