D&R Industry Articles (July 2015)
Articles for the Week of July 27, 2015
The Hard Facts about Soft Interconnect IP
Building world-class Network-on-Chip interconnect IP and configuration tools is difficult, time consuming and capital intensive- Effective Timing Strategies for Increasing PCIe Data Rates
- Chips in Space -- MacSpace, A Record Throughput Multi-Core Processor for Satellites
- Software IP Protection in a Complicated World
- Agile Design for Hardware, Part I
- Accurate and Efficient Power estimation Flow For Complex SoCs
Articles for the Week of July 20, 2015
Device Malfunction due to Faulty Digital circuit along with suggested Remedies
Using of basic building blocks in different ways to make complex circuit is a common axiom in Digital Logic design. The complexity of these building blocks can vary from simple structure like synchronizers, multiplexers, adders, FIFO, Glitch-free multiplexer to complex circuits like custom CDC Module, Encoders, decoders etc.. If we talk about these circuits, there exist countless designs, each of them depending on the requirement- any implementation working in one scenario may fail or put limitations in other scenario. This paper intends to discuss some of the commonly used circuits which are faulty in certain scenario and various remedies to make those circuits more robust to increase their acceptability.- Secure Embedded Systems: Digging for the Roots of Trust
- Cheaper, Denser NAND Requires Better Error Correction
- DDR simulation strategy catches bugs early
Articles for the Week of July 13, 2015
The Evolution of Object Recognition in Embedded Computer Vision
Object detection and recognition are an integral part of computer vision systems. In computer vision, the work begins with a breakdown of the scene into components that a computer can see and analyse.Articles for the Week of July 6, 2015
The FinFET Revolution is Changing Computer Architecture
The arrival of FinFETs, starting in the 20 nm CMOS logic process node, has been justly credited with saving Moore’s Law.- Accelerate Automotive Dev Time: Fill Hardware-in-the-Loop Gaps
- Configurable Asynchronous Set/Reset Flip-Flop for Post-Silicon ECOs
- Reset connectivity checks in complex low power architectures