D&R Industry Articles (November 2017)

Featured Article

Resolution of Interoperability challenges in Automatic Test Point insertion across different EDA vendors

For a typical design there may be some design corners where ATPG tool/algorithm may find hard to generate patterns for fault detection. This leads to loss of coverage or increase in pattern count. To overcome this issue EDA tools(DFT/ATPG) provide options to insert Control logic on locations/nodes with poor controllability or Observe test logic on locations/nodes with poor observability, these are referred as Test Points.

Featured Article

eFPGA IP Density, Portability & Scalability

There are multiple eFPGA suppliers in the market today: Achronix, Adicsys, Efinix, Flex Logix™, Menta, QuickLogic. There are 3 different business models and engineering approaches to eFPGA which you should understand to assess how it will impact your success in using their eFPGA IP and their viability as a supplier long term.

Featured Article

Ins and Outs of Assertion in Mixed Signal Verification

In this article, we demonstrate how the mixed signal assertions are different from digital assertions and how an assertion-based Verification (ABV) is extended to the Mixed Signal verification. This article also covers different assertion techniques in Mixed-Signal Verification Systems.