D&R Industry Articles (February 2019)

Featured Article

Cost Reduction and Improved TTR with Shared Scan-in DFT CODEC

This paper describes the detailed aspects of hierarchical DFT, with Shared Scan-in methodology using DFTMAX, the low pin count solution from Synopsys. The technique of sharing scan-in data between identical and non-identical cores, known as broadcasting, was employed to reduce the cost.

Featured Article

Guide to Choosing the Best LDO for Your Application

To know which LDO you need, you must first define the application of your LDO and then examine which parameters are most important when dealing with that application. With the multiple parameters that characterize a particular LDO, it is not easy to determine which LDO is best suited. To help you figure this out, we have put together this reference. This guide presents a list of all the key LDO parameters along with their definitions, the most common applications of LDOs, and which parameters are critical for each.

Featured Article

A Guide on Logical Equivalence Checking - Flow, Challenges, and Benefits

This white paper functions as a guide, outlining why LEC (Logical Equivalence Check) is important in the ASIC design cycle, how to check it, and what to do when LEC is failing.

Featured Article

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.