D&R Industry Articles (April 2019)

Featured Article

It's Not My Fault! How to Run a Better Fault Campaign Using Formal

The ISO 26262 automotive safety standard requires evaluation of safety goal violations due to random hardware faults to determine diagnostic coverages (DC) for calculating safety metrics. Injecting faults using simulation may be time-consuming, tedious, and may not activate the design in a way to propagate the faults for testing. With formal verification, however, faults are easily categorized by structural analysis providing a worst-case DC.

Featured Article

Image Processing - RTL Implementation of Median Filtering for Image Denoising

This article explains step by step implementation of Median Filtering Algorithm in Verilog. This filtering technique is then applied to noisy image for denoising. This article also explains simple Verilog based testbench and Matlab scripts for image pre/post processing operation for verifying the same.

Featured Article

Creating SoC Integration Tests with Portable Stimulus and UVM Register Models

In this article, we will explore how portable stimulus, via Accellera’s Portable Stimulus Standard (PSS), can leverage information captured in a register model to automate creation of block, subsystem, and SoC register-access tests.

Featured Article

Memory Testing - An Insight into Algorithms and Self Repair Mechanism

Conventional DFT methods do not provide a complete solution to the requirement of testing memory faults and its self-repair capabilities. A promising solution to this dilemma is Memory BIST (Built-in Self-test) which adds test and repair circuitry to the memory itself and provides an acceptable yield. This article seeks to educate the readers on the MBIST architecture, various memory fault models, their testing through algorithms, and memory self-repair mechanism.

Featured Article

Signoff Iteration Reduction Technique for Fixing Top Level Antenna

While developing large-sized chips, “divide & conquer” techniques are used. This involves partitioning the design, implementing each block individually, and stitching them together at the top level. Even if the blocks are all clean with respect to physical and timing signoff, they show incremental violations when they are stitched together.