D&R Industry Articles (June 2019)

Featured Article

Testing Of Repairable Embedded Memories in SoC: Approach and Challenges

This article focuses on how to test repairable memories when we include the repair feature, and it will also look at how it will be affected during Automatic Test Pattern Generation (ATPG) or built-in pattern generation. In addition, it focuses on the common challenges and includes a comparative case study on enabling and disabling BIRA features in memories.

Featured Article

SoC Interconnect: Don't DIY!

With so many acquisitions in the interconnect IP market, you might be forgiven for thinking DIY interconnect is a good idea.

Featured Article

Extending RISC-V ISA With a Custom Instruction Set Extension

RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows implementing precisely the instruction groups that the application needs, without having to pay for area or power that will not be used.