D&R Industry Articles (February 2020)

Featured Article

SRAM PUF is Increasingly Vulnerable

As semiconductor technology advances, SRAM is becoming outmoded as a reliable PUF security solution.

Featured Article

Layout versus Schematic (LVS) Debug

In ASIC physical implementation, once layout is generated, it must follow all the design rules for successful manufacturing and must match the schematic of the required design. To ensure this in physical verification, Design Rule Check (DRC) is carried out to check whether the layout follows the rules for fault-less manufacturing or not.

Featured Article

Choosing the Right IP for Die-to-Die Connectivity

Higher data rates and more complex functionalities are increasing the SoC size for hyperscale data center, AI, and networking applications.