D&R Industry Articles (August 2022)

Featured Article

Traceability Complements Agile Design

Agile design methods have become mainstream in software development as traditional waterfall approaches cannot scale in large, fast-moving product schedules. System-on-chip (SoC) development teams have noticed and are enthusiastically adopting similar methods to accelerate schedules and become more nimble to in-process requirement changes.

Featured Article

SoC Verification Flow and Methodologies

In this article, let me walk you through various verification methodologies we use for verifying IPs, Sub-systems, and SoCs and explain why we need new methodologies/standards like PSS.

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Synthesis Methodology & Netlist Qualification

The main objective of this article is to explain synthesis flow and post-synthesis netlist quality checks. In ASIC flow, synthesis is the part of the front-end design, while the back-end design takes the synthesized netlist as an input. So, the synthesized netlist should meet all netlist quality checks to reduce multiple iterations, which reduces the turnaround time and efforts.

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MIPI in next generation of AI IoT devices at the edge

One of the original benefits of processing in the cloud in was simply to expand beyond the limited capacity of on-site processing. With advancements in AI, more and more decisions can be made at the edge. It is now clear that edge and cloud processing are complementary technologies; they are both essential to achieve optimal system performance. Designers of connected systems must ask, what is the most efficient system partitioning between the cloud and edge?

Featured Article

A Generic Solution to GPIO verification

This paper provides a complete solution to the GPIO Verification for any SoC. GPIO interface is available in every ASIC. To avoid duplicate efforts and (save) time to verify the GPIO interface, we have produced this Generic GPIO verification suite. It is a UVM-based verification environment, with all the necessary subcomponents that are required to verify any GPIO design.