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Embedded Systems Articles

• Architecture Oriented C Optimizations (Jan. 11, 2010)
  Know your hardware! That’s what it’s all about. Using programming guidelines derived from the processor’s architecture can dramatically improve performance of C applications. In some cases, it can even make the difference between having the application implemented in C and having it implemented in assembly. Well written C code and an advanced compiler that utilizes various architectural features often reach performance results similar to those of hand written assembly code.
  
  
• What next for microcontrollers? (Jan. 06, 2010)
  The embedded world is constantly changing. One of the hottest topics in this area is when will the last of remaining 8-bit microcontroller users start to move away from legacy architectures and move to modern 32-bit processor architectures like the ARM Cortex-M based microcontroller family.
  
  
• Multicore technologies and software challenges (Jan. 04, 2010)
  Multicore processors, which are basically processors with more than one core, are entering mainstream. Today, even desktops are having two or four cores and this trend is picking up and will only accelerate in coming years. This article looks at the drivers for the multicore, the challenges posed to the software community by the emergence of multicore technologies, the different options available in software and how the software community is likely to react to the challenges.
  
  
• Legal compliance and open source software (Jan. 04, 2010)
  While open source software has become significant factor in most software development, it is not without obligations relating to licensing and copyright conditions requiring much more attention be paid to issues of legal compliance.
  
  
• How to use a debugger as a bug preventive tool (Dec. 21, 2009)
  Nathan Fields describes using a debugger as a preventive tool before you know you have a bug to track down and reviews some of the basic requirements a debugger must have to apply this technique.
  
  
• Coordinated debugging of distributed systems (Dec. 07, 2009)
  Imagine a world without a global notion of time. Now try to find out the flight direction of an airplane with the following information: There's an e-mail from Alice that she saw the plane about two hours after sunrise and another e-mail from Bob that he saw the plane about three hours after sunrise. So Alice and Bob tell us when they saw the plane, at least from their point of view. If they are nice, they might give us some additional information, namely their location at the moment of the observation. But, unfortunately embedded systems are usually not that nice.
  
  
• Boundary scan and JTAG emulation combine for advanced structural test and diagnostics (Nov. 12, 2009)
  While continuously improving IC and SoC technologies, higher clock rates, and more powerful processors are music to the design engineers' ears, the headaches of test engineers are getting worse and worse.
  
  
• Migrating ARM7 Code to a Cortex-M3 MCU (Part 2) (Nov. 02, 2009)
  In this second part, the tutorial continues with a discussion of software interrupts, fault handling, the SWP command, instruction time, assembly language, and optimizations.
  
  
• Migrating ARM7 code to a Cortex-M3 MCU (Nov. 02, 2009)
  There's a new ARM embedded core in town. Here's a step-by-step guide to porting your code to the Cortex-M3.
  
  
• Building advanced Cortex-M3 applications (Oct. 29, 2009)
  The ARM Cortex-M3 architecture provides many improvements compared with its predecessor, the popular ARM7/9, and is designed to be particularly suitable for cost-sensitive embedded applications that require deterministic system behavior.
  
  
• Using scheduled cache modeling to reduce memory latencies in multicore DSP designs (Oct. 14, 2009)
  This article describes a new software model - and hardware mechanisms that support it - used in the Freescale SC3850 StarCore DSP subsystem residing in the MSC8156 multi-core DSP. Called the scheduled cache model,, it reduces the need for DMA programming and synchronization to achieve high core utilization.
  
  
• Embedded software development using an interpretive instruction set simulator (Oct. 12, 2009)
  This paper presents an instruction set simulator of an 8-bit, MCS-51 compatible CPU core, and shows how to use it in embedded software development process; Method to control and debug CPU using embedded Tcl script interpreter via universal debug interface is also discussed.
  
  
• Building a standard micro architecture (Oct. 07, 2009)
  Many microcontroller architectures have a long history, with most 8 and 16 bit architectures being designed more than 20 years ago. Over the years these architectures have been re-shaped several times to incorporate new technological developments and keep pace with the industries ever-increasing demands.
  
  
• Multicore programming made easy? (Sep. 24, 2009)
  The first multicore platforms have found their way into embedded systems for entertainment and communication, especially thanks to their greater computational power, flexibility, and energy efficiency. However, as we will show, mapping applications onto these systems remains a challenge that is costly, slow, and prone to errors.
  
  
• Fundamentals of Booting for Embedded Processors (Sep. 21, 2009)
  There are multiple ways to boot, multiple purposes behind booting, and multiple factors that affect the process. David Katz and Rick Gentile explore these issues in an attempt to deliver a clearer overall picture of what is entailed by the embedded booting process.
  
  
• Seamless integration of multicore embedded systems (Sep. 21, 2009)
  This paper presents a seamless and continuous integration approach that allows to gradually introduce performance improvements while preserving an established functional baseline in an embedded system with demanding characteristics requirements. The following topics will be addressed: how performance improvements can be broken down in small steps with objective and measurable goals, how to predict, verify and measure them.
  
  
• Evaluating the performance of multi-core processors - Part 2 (Sep. 17, 2009)
  One common question when customers review data from microprocessor benchmarks such as those discussed in Part 1 is "How well will benchmark performance predict my particular application's performance if I employ your new processor or new compiler?"
  
  
• Evaluating the performance of multi-core processors - Part 1 (Sep. 17, 2009)
  Determining the specific multi-core processor that will suit your embedded application needs is a challenge. Relying upon the marketing collateral from a given company is not sufficient because in many cases, the results quoted are specific to a given platform and ambiguous application; there is no guarantee your application will exhibit the same performance.
  
  
• Anti tamper real time clock (RTC) - make your embedded system secure (Sep. 14, 2009)
  This article describes some of the techniques that can be well handled by a real time clock (RTC) within a system on chip (SoC) by providing efficient protection against hardware as well as software tampers, thereby making it an essential item in every secure system.
  
  
• Cost-effective SoCs are the key to fostering innovation (Sep. 09, 2009)
  Innovation is being stifled by the lack of options for chip design implementation. Innovation entails trying the unknown. It's an evolutionary process in which something new is tested, then refined as market preferences become clear.
  
  
• Using platform independent models to proliferate code across multiple application environments (Sep. 09, 2009)
  With Platform Independent Modeling allows an embedded design can be developed and validated independently of the development of application code, allowing the software team to focus on developing optimized source code for the selected target architectures.
  
  
• Why Hi-Speed USB doesn't always mean high speed performance (Sep. 02, 2009)
  With Hi-Speed USB being an essential requirement for new media-centric electronics devices, designers have the choice of ways to support it. The trick is picking the right architecture.
  
  
• H.264 Baseline Encoder with ADI Blackfin DSP and Hardware Accelerators (Aug. 27, 2009)
  In this paper, architecture and implementation of H.264/AVC baseline en coder for D1 resolution at 30fps using ADI Blackfin DSP and Hardware accelerators in FPGA is described. FPGA accelerators perform the processing required till generation of the Quantized coefficients (Loop1) for the Blackfin DSP to perform the entropy coding (Loop2). Bit rate control and quantization parameter (Qp) calculation is performed in the DSP while FPGA provides the frame level parameters to ADSP for acceleration of bit rate control, and calculation of Qp.
  
  
• PRODUCT HOW-TO: Debugging hardware designs with an FPGA-based emulation tool (Aug. 25, 2009)
  Ludovic Larzul of EVE describes how embedded systems developers can lower the cost of hardware debugging on their ASIC, FPGA and SoC designs through the use of an FPGA-based emulation tool.
  
  
• Image stabilizers: Utilizing DSP for more advanced, scalable stabilization algorithms (Aug. 20, 2009)
  How Human Monitoring's "Leonardo" image stabilization technology takes advantage of TI's DaVinci processor to bring high performance image stabilizing to mass-market cameras. A case study.
  
  
• Serial Boot - An alternative and effective way of booting SoC externally (Aug. 13, 2009)
  This article deals with the Serial boot protocol and preparing a boot code for the serial booting. It tells about the things to take care while generating the boot code and the process of booting up the device using serial protocol. LIN and CAN are the common communication protocols being used in the automotive MCUs for serial booting.
  
  
• Virtual multi-cores simplify real-time system design (Jul. 30, 2009)
  Systems comprising many small cores are well suited to handling complex real-time tasks, offering a software development cycle in which real-time tasks are allocated to (virtual) cores, each guaranteed to adhere to real-time constraints.
  
  
• Building a software test and regression plan (Jul. 23, 2009)
  How Mirabilis Design developed a comprehensive test and support plan for its VisualSim graphical environment used to create virtual environments for evaluating application performance and size the hardware platforms.
  
  
• Implementing the Viterbi Algorithm in Today's Digital Communications Systems (Jul. 16, 2009)
  Though multimedia content may push the limits of digital communications systems, the Viterbi forward error correction algorithm remains the most effective way of overcoming channel noise. In this feature, CEVA describes how the algorithm works and gives a practical demonstration of how to implement it, using the TeakLite III DSP platform as an example.
  
  
• Securing SoC Platform Oriented Architectures with a hardware Root of Trust (Jul. 08, 2009)
  As platform-oriented-architecture-based devices incorporate the product feature and service configuration and management the need to secure them and the systems they support makes a hardware-based "root of trust" a critical requirement.