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Embedded Systems Articles
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Selecting memory controllers for DSP systems (May. 14, 2007)
DSP system performance is often limited by I/O constraints. Here's how to make sure your memory system meets your latency requirements.
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Audio Coding for Wireless Applications (May. 10, 2007)
This paper discusses wireless audio transmission and the issues that need consideration, and suggests the apt-X algorithm as an appropriate and advantageous coding solution.
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How to choose an RTOS for your FPGA and ASIC designs (May. 10, 2007)
As an alternative to purchasing an off-the-shelf RTOS or writing your own, a new software synthesis technique called RTOS synthesis may be of interest for certain applications
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How to write an optimized FIR filter (Apr. 23, 2007)
This article shows how to write optimized FIR filter code for a DSP, using the Texas Instruments C55x architecture as an example.
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Hardware and software don't matter (Apr. 19, 2007)
The typical DSP design process has three basic elements: Algorithm design, hardware design, and software design. Similarly, most DSP engineers think of themselves as belonging to one of three groups: Algorithm designers, hardware designers, or software designers.
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Going multicore presents challenges and opportunities (Apr. 10, 2007)
Performance and power efficiency are key advantages, but they're also challenging as the number of cores increases.
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Integrating and evaluating speech algorithms (Apr. 02, 2007)
Designing and developing an embedded system from scratch and making it stable is always a challenge. Integrating and evaluating a digital signal processing (DSP) algorithm with the system is equally tricky and can bring even the strongest programmers to their knees. Today, uncountable numbers of algorithms are embedded into various electronic systems. How does an embedded system developer know which algorithm to use for speech processing, such as that found in basic telephony systems?
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Using sub-RISC processors in next generation customizable multi-core designs: Part 1 (Mar. 29, 2007)
The now-common phrase ''the processor is the NAND gate of the future'' begs the questions: ''What kind of processor?'' and "How to program them?'' When this is discussed, the focus is usually placed on RISC-based processors augmented with instruction extensions as the natural building block. The presumption is that programming will be done in the C language.
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Open Source FlexRay Communication: Time Triggered OS and FlexRay Communication Middleware (Mar. 15, 2007)
We developed a set of software programs for FlexRay communication, which is considered the next de facto standard for automotive communication, and we will release our programs as open source software in near future. For the programs mentioned above, we have decided to develop specifications for a time triggered real time operating system that is suitable for FlexRay communication middleware. This operating system has a special feature which manages both time triggered control and event triggered control
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The basics of HD H.264 and next-generation encoding (Mar. 08, 2007)
There are several solutions available to meet the challenges of HD video encoding, including PC platforms, FPGAs, dedicated ASIC/System on-chip codecs, and DSPs. We discuss the benefits and costs of each of these solutions, and draw on Telairity's experience in developing its H.264 HD real-time encoders to highlight the importance of programmable architectures for encoding solutions that deliver long-haul viability.
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Using PCIe in a variety of multiprocessor system configurations (Jan. 22, 2007)
PCI Express (PCIe), like the legacy PCI bus it evolved from, was architected to serve as a simple DMA I/O subsystem for a single host processor.
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DVB-H handheld video content protection with ISMA Encryption (Jan. 08, 2007)
An introduction to DVB-H service protection with a strong emphasis on ISMA Encryption and Authentication, Version 1.1 (also known as ISMACryp 1.1), recently finalized by the Internet Streaming Media Alliance.
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Five things to keep in mind when selecting an embedded mobile/consumer SoC (Dec. 18, 2006)
Here are five things to consider when selecting SoC processors for your embedded systems
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Tutorial: Programming High-Performance DSPs, Part 1 (Nov. 27, 2006)
This first of a three-part series explains the features of high-performance DSPs, with a focus on VLIW pipelines and multi-level memory architectures. It shows how to write code for these advanced architectures. It also introduces Direct Memory Access (DMA), and explains how to use it.
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Achieving multicore performance in a single core SoC design using a multi-threaded virtual multiprocessor: Part 2 (Nov. 27, 2006)
The key to the Virtual Processor Element (VPE) approach used in the MIPS 34K core is a set of extensions of the processor's basic instruction set architecture, rather than a specific set of hardware features to enable efficient multi-threading.
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Using high integration SoC alternatives for your legacy X86 design (Nov. 20, 2006)
During the past several years End-of-Life (EOL) notices for most legacy x86 processors have increased dramatically leaving many OEMs producing products for the embedded market with few choices other than significant system redesign.
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Optimizing the Implementation of Dolby Digital Plus in SoC Designs (Nov. 16, 2006)
This white paper outlines the benefits of Dolby Digital Plus for select key consumer audio markets and details the processes behind the collaborative effort between MIPS Technologies and Dolby Laboratories.
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Integrating an H.264 video encoder with Stretch's processor (Nov. 13, 2006)
Using the Vanguard Software Services (VSS) H.264 Encoder for Stretch Software Development Kit (SDK) as the basis for adding an H.264 encoder to your application.
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Embedded multicore needs communications standards (Nov. 08, 2006)
Multicore systems are popular but problematic. The authors describe the problem with communications APIs and what the Multicore Association is doing about it
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Tech Tutorial: Message buffers provide FlexRay versatility (Nov. 06, 2006)
Here is what is needed in hardware and software to configure, control, and monitor message buffers to meet a system's required deterministic latency and fault tolerance
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Designing An ARM-Based Multithreaded Video/Audio/ Motion Recording System - Part 2 (Oct. 23, 2006)
Our implementation will be simplified because we are primarily interested in developing a control structure for this system. Thus, we will omit all file handling details, represent files as arrays, and simulate capture of data once per second.
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Designing An ARM-Based Multithreaded Audio/Visual/Motion Recording System: Part 1 (Oct. 16, 2006)
Our design provides the ability to record several events within each 24-second time frame, rather than just one. Application timers play a major role in providing this feature. We also used application timers to simulate interrupts that signify the occurr
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Multi-core MPEG-4 video encode partitioning (Oct. 09, 2006)
Partitioning a video-encoding algorithm onto a multi-core architecture can utilize a variety of techniques, including data partitioning and pipelining. Cradle Technologies explains them, and how to do MPEG-4 Baseline Profile implementation on their multi-
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Migrating from 8-/16-bit to 32 bit: Lessons Learned the Hard Way (Sep. 25, 2006)
Processors are becoming more powerful both in terms of the MIPS and the bandwidth of the data they can handle. They are equipped with most of the peripherals to make them resemble a System on a chip (SoC). As the complexity rises it is difficult to compre
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Quad-core DSP for mobile video gateway system design (Sep. 25, 2006)
Even a basic 3G-324M gateway supporting only H.263 and MPEG4 requires a lot of processing power. Multi-core devices have design advantages
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Software Certifications and Standards: What Every Device Manufacturer Should Know (Sep. 21, 2006)
The mandate for certified safe and secure software used to be the exclusive domain of military, medical and government or other niche areas. New regulations are beginning to play a critical role in the viability of devices manufactured for the global mark
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Complex ASSP Devices: Handle increased complexity (Sep. 18, 2006)
Advanced telecommunications silicon integrates a wide variety of functions and interfaces to spread the high costs of device development across as many applications as possible, but this trend increases device complexity
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ARM11 MPCore Provides Existing Software Portability Across Single- CPU and Multi-CPU Designs (Sep. 14, 2006)
The ARM11 MPCore synthesizable processor implements the ARM11 microarchitecture and can be configured to contain between one and four processors delivering up to an aggregate 2600 Dhrystone MIPS of performance.
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Criteria for ARM Migration as the Industry Standard MCU (Aug. 24, 2006)
This article reviews available tools as well as design advantages and challenges engineers will need to consider when designing MCUs based on the ARM architecture.
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How to use ARM's data-abort exception (Aug. 24, 2006)
This in-depth article explains the hows and whys of data aborts on the ARM7 family of processors, including working code for a useful data-abort exception handler.