Foundries Articles

• 20nm Dilemma Explained (Apr. 07, 2014)
  Fully depleted silicon-on-insulator is the best solution for the 28nm and 20nm technology nodes because of its lower cost and leakage and higher performance than bulk CMOS.
  
  
• Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond (Feb. 21, 2013)
  What sort of features and computing capabilities will we expect of our mobile devices five years from now? How about in 10 years?
  
  
• Fully Depleted Silicon on Insulator devices (Jun. 20, 2012)
  For decades, we rode the technology wave by building smaller and smaller transistors into a bulk silicon wafer. Around 90nm, we began to realize that there were problems ahead as voltage scaling slowed and leakage currents increased.
  
  
• New IC verification techniques for analog content (Nov. 18, 2010)
  Increasing numbers of integrated circuits (ICs) are targeted at mobile/wireless applications. The amount of analog content in these designs increases as designers integrate more functions such as WiFi, Bluetooth, 3G, GPS, and audio. The difficulty of verifying these designs is compounded by the fact that the chip designer may be including analog IP from outside sources.
  
  
• IP/foundry ecosystem facilitates 45-nm process design (Jul. 27, 2007)
  To overcome 45-nm process challenges, semiconductor intellectual property (IP) providers and foundries are collaborating to provide designers with a combination of design resources and manufacturing expertise focused on advanced process nodes. TSMC and Virage Logic are proactively collaborating on 45-nm process and IP development so designers can make best use of the growing IP-foundry ecosystem.
  
  
• Designing ICs with the 'X' Architecture (Aug. 29, 2005)
  The X Architecture represents the pervasive use of both Manhattan and diagonal interconnect on a chip.
  
  
• SOI eases radiation-hardened ASIC designs (Jul. 25, 2005)
  Authors from Honeywell and Synopsys show how silicon-on-insulator makes it easier to create rad-hard ICs, and discuss the design techniques and practices needed for radiation hardening.
  
  
• Design myths surround strained SOI (Apr. 12, 2004)
  Design myths surround strained SOI
  
  
• Strained SOI on the move to mainstream (Dec. 22, 2003)
  Strained SOI on the move to mainstream
  
  
• Modeling challenges for 90 nm and below (Sep. 18, 2003)
  Modeling challenges for 90 nm and below
  
  
• ASIC technology is morphing as demand for custom chips remains solid despite rising mask costs and slow growth in many end markets. (Aug. 04, 2003)
  ASIC technology is morphing as demand for custom chips remains solid despite rising mask costs and slow growth in many end markets.
  
  
• Times are tough all over, so don't write off the silicon foundry model just yet (Apr. 28, 2003)
  Times are tough all over, so don't write off the silicon foundry model just yet
  
  
• 90 nm requires collaboration on design rules (Mar. 31, 2003)
  90 nm requires collaboration on design rules
  
  
• Taking on the 130nm node and beyond (Jan. 13, 2003)
  Taking on the 130nm node and beyond
  
  
• Foundries wield intellectual property to gain an edge (Dec. 23, 2002)
  Foundries wield intellectual property to gain an edge
  
  
• SEMI survey shows '02 fab-tool market to fall 32% (Dec. 06, 2002)
  SEMI survey shows '02 fab-tool market to fall 32%
  
  
• China could make 5% of chips in 2010, says study (Nov. 27, 2002)
  China could make 5% of chips in 2010, says study
  
  
• Foundries appear to break laws of economics (Nov. 13, 2002)
  Foundries appear to break laws of economics
  
  
• Dataquest sees slow silicon wafer market; downturn changes vendor rankings (Jun. 03, 2002)
  Dataquest sees slow silicon wafer market; downturn changes vendor rankings
  
  
• Is foundry broker model the next thing in fabless business? (May. 24, 2002)
  Alpha Technologies
  
  
• "You didn't want to do that..." (Apr. 18, 2002)
  "You didn't want to do that..."