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FPGA / CPLD Articles

• Platform FPGA design for high-performance DSPs (Apr. 11, 2006)
  This tutorial explains how Platform FPGAs can be used to meet the challenges of today's demanding high-performance real-time DSP applications
  
  
• DSP design flows in FPGAs: Strategies for designing DSP applications for FPGAs (Apr. 05, 2006)
  Digital signal processing (DSP) occurs in communications, audio, and multimedia devices, imaging and medical equipment, smart antennas, automotive electronics, MP3 players, radar and sonar, and barcode readers, to name but a few.
  
  
• FPGA partial reconfiguration mitigates variability (Apr. 03, 2006)
  For logic design, this means the hardware must be able to handle a variety of functions, which leads to more devices and more real estate. A common method to handle this additional functionality has been to move them into switchable software modules handl
  
  
• C-Language techniques for FPGA acceleration of embedded software (Mar. 31, 2006)
  This paper presents a brief overview of modern FPGA-based platforms and related software-to-hardware tools, then moves quickly into a set of examples showing how computationally-intensive algorithms can be written, analyzed and optimized for increased per
  
  
• FPGAs for prototyping - ASICs for production (Mar. 28, 2006)
  This ''How To'' describes the items that must be considered during the initial FPGA design flow in order to ease a subsequent FPGA-to-ASIC migration.
  
  
• All about FPGAs (Mar. 23, 2006)
  An industry expert examines field-programmable gate arrays (FPGAs), including current and forthcoming architectures, technologies, and software tools.
  
  
• What to know when designing with high-performance FPGAs (Mar. 09, 2006)
  Leading-edge programmable logic applications are requiring larger and larger amounts of logic and I/Os, arising from an increasing number of core functions being partitioned into the FPGA. Such high-performance systems typically have a variety of high-ban
  
  
• Real-Time Video System Design Based on the NIOS II Processor and µCLinux (Feb. 09, 2006)
  Real-Time Video System Design Based on the NIOS II Processor and µCLinux
  
  
• Compiling FPGA netlists for formal verification (Feb. 06, 2006)
  Due to the ever increasing demand for more speed, less area, and less power, the transformation of a customer’s RTL description into a bitstream format that can program the FPGA is increasingly complicated. This in turn increases the demand for verifying
  
  
• FPGAs add flexibility to communications traffic management (Feb. 01, 2006)
  A 10-Gbps FPGA-based traffic manager solution meets the demands of next-generation networks by supporting high-speed throughput in a solution that can adapt to the changing market.
  
  
• Optimizing DSP functions in advanced FPGA architectures (Jan. 25, 2006)
  This paper outlines practical steps, along with common mistakes to avoid, for successfully extracting optimal results in your DSP-based FPGA designs.
  
  
• Meeting signal integrity requirements in FPGAs with high-end memory interfaces (Jan. 18, 2006)
  As valid signal windows shrink, signal integrity (SI) becomes a dominant factor in ensuring that high-end memory interfaces perform flawlessly.
  
  
• Maximizing performance in FPGA systems (Jan. 02, 2006)
  With programmable hard intellectual property like DSP building blocks, serdes and embedded processors, FPGAs have become complex systems-on-chip. As a result, extracting higher performance involves far more than just cranking up the fabric clock rate.
  
  
• A practical approach to reusing HDL code in FPGA designs (Dec. 29, 2005)
  The industry is driving toward enabling design for reuse with standards, presentations, and pleas. Smart FPGA designers, however, have realized that it is more practical to recycle existing HDL code. This paper discusses how to reuse existing code that wa
  
  
• How to use register retiming to optimize your FPGA designs (Dec. 14, 2005)
  This article outlines recommended practices that show you how to qualify an FPGA-based design as a good candidate for register retiming, along with specific examples for optimal performance results.
  
  
• Network require multi-gigabit processing? Try multi-core FPGAs (Dec. 05, 2005)
  The use of a multi-core array of embedded soft processors on an FPGA allows for multi-gigabit processing, quick design, and system longevity. Here's how.
  
  
• How to reduce costs by integrating PCI interface functions into CPLDs (Nov. 30, 2005)
  Programmable logic-based PCI interface solutions offer significant advantages over ASSPs in terms of cost, board space reduction, flexibility, and obsolescence-proofing.
  
  
• Power considerations in designing with 90 nm FPGAs (Nov. 23, 2005)
  This ''How To'' article explores the various power considerations that can be addressed by the FPGA vendor and the end user.
  
  
• Ensuring Serial Protocol Signal Integrity with FPGAs and Embedded Transceivers (Nov. 17, 2005)
  Today’s high-end field programmable gate arrays (FPGAs) with embedded transceivers support a variety of widely accepted serial protocol standards, including Gigabit Ethernet, PCI Express, XAUI and Serial Rapid IO
  
  
• Building an FPGA FIFO without using logic recourses (Nov. 07, 2005)
  This article describes how to build a full-featured FIFO in an FPGA without consuming valuable logic resources.
  
  
• Dual-port FPGA memory blocks: the ultimate system interconnect solution? (Nov. 03, 2005)
  This article evaluates the validity of FPGA vendors' claims by taking the reader through a recent benchmarking effort on integrated dual-ports in FPGAs
  
  
• Secure in-system programming for FPGAs (Oct. 27, 2005)
  Controlling access to - and protecting the intellectual property inside - an FPGA is a requirement known as Secure ISP
  
  
• Low-power PLDs: A Good Choice for Portable Designs (Sep. 26, 2005)
  This article uncovers real power and cost savings, and describes how to harness the key features of low-power PLDs.
  
  
• Do's and Don'ts of Architecting the Right FPGA Solution for DSP Design (Sep. 13, 2005)
  Finally a Practical ''Do and Don't'' primer on architecting FPGA solutions for DSP design. With more do's than don’ts, the article is a down-to-basics look at how to avoid the pitfalls and realize device benefits
  
  
• Implementing DSP Functions Within FPGAs (Sep. 07, 2005)
  Industry gurus Cofer and Harding explain how to understand the overall design cycle, development tools, and make good design decisions and avoid implementation missteps
  
  
• How To Interface DDR-II SRAMs with Stratix II Devices (Sep. 07, 2005)
  This article is a step-by-step guide to interfacing DDR-II SRAMs with Stratix II devices for high-bandwidth communications, networking, and DSP applications
  
  
• How to Protect Intellectual Property in FPGAs Devices--Part 1 (Aug. 24, 2005)
  IP theft is becoming a major problem. Estimates are that 186 counterfeit ICs are available. Protect your FPGA IP. Here's the first installment of a two-part article showing you how
  
  
• How to Integrate Flash Device Programming and Reduce Costs (Aug. 17, 2005)
  In the late 1980s memory devices changed in a flash. Intel and Toshiba spearheaded the development of flash process technology to create a new class of products
  
  
• Programmable System Chips: An alternative to MCU-based designs? (Aug. 10, 2005)
  End applications continue to demand increased flexibility, configurability and performance, along with reduced power demands, board space and cost
  
  
• Back to the basics: Programmable Systems on a Chip (Jul. 27, 2005)
  By way of a short refresher, each FPGA vendor has its unique FPGA architecture. All are, however, in general terms, a variation of that shown in Figure 1