FPGA / CPLD Articles
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2.5D ICs are more than a stepping stone to 3D ICs (Mar. 28, 2012)
The vision of a 3D IC is truly promising, but some industry watchers believe the 2.5D market is perhaps being too easily dismissed as a stepping stone to true 3D design. 2.5D has the distinct advantage of being already here today for some companies--and leveraging it takes only minor adjustments to current design flows and seemingly the manufacturing chain.
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An FPGA-based dual-image sensor design solution (Mar. 28, 2012)
When one thinks about an application with two image sensors, the first thought is likely to be a 3D camera. However, there are numerous designs that can be improved by using the data from two image sensors.
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FPGAs unleash potential of Flash memory for enterprise applications (Mar. 19, 2012)
Enterprise storage subsystems today are undergoing an essential transformation. The sheer volume of enterprise data and transactions is increasing by as much as 50-60% per year. The rapid proliferation of cloud computing and virtualization as a means to more efficiently manage these burgeoning data workloads has spawned explosive growth in the number and size of data centers. Along with the exponential growth in enterprise storage comes an imperative to improve memory subsystem performance capacity and value.
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2.5-D will be a market of its own (Mar. 01, 2012)
Leveraging 2.5-D industrywide will require evolutionary, rather than revolutionary, adjustments to current design flows and the supply chain.
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FPGA-based Ethernet switches for real-time applications (Feb. 27, 2012)
Lattice Semiconductor and Flexibilis have released a Gigabit Ethernet Switch IP core that is scalable, non-blocking, and extensible
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How to build a self-checking testbench (Feb. 27, 2012)
Here’s quick example to illustrate how to implement a testbench using a simple 8-bit up/down with reset as the FPGA design (UUT). The testbench provides clock, up/down, enable and reset control signals.
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PowerSoC solves switch-mode DCDC noise and space issues (Feb. 06, 2012)
This article describes the various components of noise in a switch-mode DCDC converter and demonstrates how PowerSoCs can minimize those components. The article further shows design examples and demonstrates how PowerSoCs can power high speed IO with performance equivalent to or better than Linear Regulators.
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Programmable logic, SoC simplify power steering, accessory control (Jan. 31, 2012)
This article discusses the design of a control system featuring a microcontroller plus ASIC or microcontroller plus programmable logic SoC for an automotive electric power steering system. Such a system receives the "ignition" (steering "drive" command) input from the user plus vehicle inputs through a CAN transceiver and drives a three-phase brushless motor.
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Single event effects (SEEs) in FPGAs, ASICs, and processors, part I: impact and analysis (Dec. 15, 2011)
Single-event effects (SEEs) are of a growing concern in high-reliability system development, yet there is much disparity among users of application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) with regard to understanding how susceptible their designs might be.
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Using FPGAs to solve challenges in industrial applications (Nov. 23, 2011)
This article describes the trends and challenges seen by designers of industrial applications and how FPGAs enable solutions to meet their stringent design goals.
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How to build a better DC/DC regulator using FPGAs (Nov. 03, 2011)
The availability of low-cost FPGAs and ADCs allows digital control of switch-mode DC/DC regulators.
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Creating the Xilinx Zynq-7000 Extensible Processing Platform (Oct. 18, 2011)
In March of 2011, Xilinx officially announced the first four devices of its new 28nm Zynq-7000 Extensible Processing Platform (EPP) family. Each of these devices merges an ARM dual-core Cortex-A9 MPCore processing system with a NEON media engine and a double-precision floating-point unit on the same IC, along with Level 1 and Level 2 caches, memory controllers, large programmable-logic blocks and a slew of commonly used peripherals.
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5 Wirebond Power Bus Watch Out! (Sep. 12, 2011)
Wirebond package,lower cost package with lesser IO density always impose challenge for FPGA designer to meet the required power parameteric budget.This paper will share 5 watch outs on wirebond chip power bus planning.
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How do I reset my FPGA? (Aug. 11, 2011)
Devising the best reset structure can improve the density, performance and power of your design.
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Designing with core-based high-density FPGAs (Aug. 01, 2011)
This article presents Robert S. Grimes' experience with designing a nontrivial multiprocessor system, using three networked Xilinx Virtex-4FX-based controllers.
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How to accelerate genomic sequence alignment 4X using half an FPGA (Jul. 11, 2011)
C-based approach shortens time to accelerate processing on FPGA hardware
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Medical imaging process accelerated in FPGA 82X faster than software (Jun. 30, 2011)
Line of reaction (LOR) estimation for a PET scanner optimized using C-to-FPGA methodology
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Zynq-7000 EPP sets stage for new era of innovations (Jun. 20, 2011)
Xilinx's Zynq-7000 Extensible Processing Platform family mates a dual ARM Cortex-A9 MPCore processor-based system with programmable logic and hardened IP.
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Designing remote radio heads (RRHs) on high-performance FPGAs (Feb. 08, 2011)
Current and future generations of wireless cellular systems feature heavy use of Remote Radio Heads (RRHs) in the base stations. This article discusses using FPGAs to implement RRHs.
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Hardware-based floating-point design flow (Feb. 07, 2011)
This paper describes a new approach to efficiently implementing a floating-point algorithm in a hardware FPGA architecture that achieves extremely high rates of floating-point processing (at least 1 TeraFLOPS) in a single FPGA die, and with significantly better power efficiency than the microprocessor-based alternatives.
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Free I/O: Improving FPGA clock distribution control (Jan. 24, 2011)
This article examines offers practical advice for designers who are considering ways to enable additional FPGA I/O, or improve clock network performance.
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Scalable architectures for high-bandwidth Ethernet line cards (Jan. 13, 2011)
As more consumers receive streaming video in various formats over the Internet, demand for bandwidth continues to increase. However, consumers watching streaming movies via their Xbox or Wii, or viewing YouTube on their computers, are not paying more for the additional gigabits they download each month watching these video feeds. This is one of many factors fueling the demand for higher bandwidth while yielding lower price per gigabit of bandwidth.
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Using mixed-signal FPGAs to take motion control to the next step (Dec. 13, 2010)
Designers of motion control systems now have the opportunity to develop single-chip solutions for controlling even complex motors with SmartFusion devices.
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Building FPGA-based digital downconverters with graphical design tools (Dec. 09, 2010)
Graphical programming tools and commercial, off-the-shelf hardware have progressed to the point that they can be used to implement high-performance designs with minimal FPGA-specific knowledge.
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Practical Case: Embedded Multiprocessor Design on a Flexible Hardware: NEO_CORE_CYCLONE_III (Dec. 06, 2010)
ADENEO's customer needs, in Power Converting sector, are often similar. Differences are mainly focused on power gate driving, system interfaces and monitoring. It is obvious that generic development enables leverage across various designs, allowing us to focus on specific design related to customer needs
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IP in FPGAs: Blessing and a curse (Nov. 24, 2010)
One of the largest confabs in the still-maturing semiconductor IP industry happens next week. The IP-SoC 2010 event in Grenoble, France, has been a long-standing meeting point (19 years and counting) for those in and around the IP business. The strength of the technical sessions and the level of attendance is a tribute to the folks at Design & Reuse who started the event many years ago.
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DSP options to accelerate your DSP+FPGA design (Oct. 25, 2010)
Although signal processing is usually associated with digital signal processors, it is becoming increasingly evident that FPGAs are taking over as the platform of choice in the implementation of high-performance, high-precision signal processing.
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How to reduce board management costs, failures, and design time (Oct. 13, 2010)
In order to meet the demands of increased functionality, performance, and reduced power, many modern circuit boards use highly integrated CPUs, ASSPs, ASICs, and memory devices to implement the circuit board’s main function (the payload function).
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The "Long Tail" of FPGAs (Oct. 06, 2010)
Since their introduction in the mid-80s, FPGAs have managed to wedge themselves as a fixture into the electronics design landscape. Sitting somewhere between off-the-shelf (OTS) logic, ASICs, OTS processors, and ASSPs, they continue to enjoy growth predictions beyond those of the rest of the semiconductor industry.
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What! How big did you say that FPGA is? (Team-design for FPGAs) (Sep. 28, 2010)
When FPGAs deliver the equivalent of a 20- to 30-million gate ASIC, FPGA design tools, which have traditionally been used by just one or two engineers on a project, begin to break down.