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FPGA / CPLD Articles

• Focus on FPGA programmable platform for industrial systems (Nov. 30, 2006)
  FPGAs provide greater industrial design flexibility
  
  
• Speed up downconverter implementation with rapid prototyping (Nov. 13, 2006)
  Using the right EDA tools, performance can be simulated, analyzed and design characteristics automatically converted to generic HDL code appropriate for synthesis and FPGA implementation.
  
  
• Tap into the advantages of a scalable OFDMA engine for WiMAX (Nov. 09, 2006)
  A scalable orthogonal frequency-division multiple access (OFDMA) engine for mobile worldwide interoperability for microwave access (WiMAX) can be used to accelerate the development of mobile broadband wireless networks based on the IEEE 802.16 standard.
  
  
• How to get more performance in 65 nm FPGA designs (Nov. 08, 2006)
  This ''How To'' explores how FPGA designers can benefit from the latest FPGA building blocks in their quest for higher system-level performance.
  
  
• Special Preview: BDTI's FPGAs for DSP, Second Edition (Nov. 06, 2006)
  In this article we present insights gained from our benchmarking and analysis, focusing on the evolving role of FPGAs and other implementation technologies targeting digital-signal-processing-intensive applications.
  
  
• Accelerating Architecture Exploration for FPGA Selection and System Design (Oct. 30, 2006)
  
  
  
• How to tackle serial backplane challenges with high-performance FPGA designs (Oct. 26, 2006)
  Flexible FPGA fabric, embedded multi-gigabit transceivers, and off-the-shelf IP enable robust, high performance, and high-integration serial backplane interface solutions
  
  
• How to utilize advanced FPGA features without getting locked into an architecture (Oct. 18, 2006)
  A vendor-independent design approach that allows design development independent of the target FPGA architecture can pay big dividends.
  
  
• How to use FPGAs to implement MOST in automobiles (Oct. 09, 2006)
  Programmable FPGA-based solution from Xilinx and Mocean brings architectural flexibility to MOST (Media-Oriented System Transport)-based multimedia systems in automobiles
  
  
• Verify timing of parallel PHY interfaces for Gigabit Ethernet (Oct. 05, 2006)
  Focusing on such standard parallel PHY interfaces for Gigabit Ethernet as RGMIIv2.0, RGMIIv1.3, and GMII, here is an analytical approach showing how to transform timing specs to design constraints, and a methodology to verify adherence to timing specs usi
  
  
• How to design and verify mixed-signal FPGAs (Oct. 05, 2006)
  A 'smart' system design and verification flow for mixed-signal FPGAs helps digital designers overcome the complexities of the analog domain.
  
  
• How to use CPLDs to manage average power consumption in portable applications (Sep. 28, 2006)
  Many designs are challenged by the battery resources of an application. Batteries are limited charge reservoirs with varying capabilities on voltage regulation. Each battery has its own qualities for delivering charge. Many batteries can deliver high curr
  
  
• How to reduce power using I/O gating (CPLDs) versus sleep modes (FPGAs) (Sep. 21, 2006)
  Understanding the differences between low power CPLDs (that use built-in I/O gating features to save power) and non-volatile FPGAs (that employ ''Sleep Modes'').
  
  
• Analyze DSP algorithms in FPGAs fast with z-transform (Sep. 20, 2006)
  Crafting DSP algorithms for optimum performance in hardware often requires sophisticated design techniques, such as pipelining and overclocked control logic. Such is the case for implementations using the Xilinx Virtex-4 DSP48 slice, which attains maximum
  
  
• How to get the best performance and utilization from Xilinx Virtex-5 FPGAs (Sep. 14, 2006)
  In order to obtain the best performance and efficiently utilize the capacity offered by Virtex-5 FPGAs, it is necessary to use the right synthesis technology.
  
  
• FPGA Architectures from 'A' to 'Z' : Part 2 (Sep. 11, 2006)
  If you are new to FPGAs, there are a bewildering number of different architectures and related concepts; but fear not, because this tutorial explains all.
  
  
• How to use FPGAs to implement high-speed RLDRAM II interfaces (Aug. 31, 2006)
  RLDRAM II devices bridge the gap between DDR SDRAM and SRAM; FPGAs offer a solution that enables FPGA-to-RLDRAM II interface performance to run up to 300 MHz.
  
  
• A tutorial on incremental design using FPGAs from Actel (Aug. 28, 2006)
  An ''incremental'' design flow is highly desirable with regard to repairing or optimizing parts of the design without disturbing portions that have met their design requirements
  
  
• FPGA Architectures from 'A' to 'Z' : Part 1 (Aug. 16, 2006)
  If you are new to FPGAs, there are a bewildering number of different architectures and related concepts; but fear not, because this tutorial explains all.
  
  
• Designing control circuits for FPGA-based DSP systems (Aug. 11, 2006)
  If you need to design a control circuit for your FPGA-based DSP system, these simple techniques could save you days of work.
  
  
• How to accelerate algorithms by automatically generating FPGA coprocessors (Aug. 10, 2006)
  Recent advances in C-to-FPGA design methodologies and tools facilitate the rapid creation of hardware-accelerated embedded systems.
  
  
• Rapid Prototyping and Verification of MIMO Systems (Aug. 03, 2006)
  A practical approach to system implementation using MATLAB and Virtex-4 FPGAs.
  
  
• Video and image processing design using FPGAs (Jul. 07, 2006)
  FPGAs are an ideal fit for video and image processing applications where there is a need to have a scalable solution for improving cost, performance, and flexibility while meeting time-to-market goals.
  
  
• How to speed FPGA debug with measurement cores and a mixed-signal oscilloscope (Jun. 29, 2006)
  In this article, we will look at an approach that allows the combination of these measurements through the use of an Agilent mixed signal oscilloscope (MSO) in conjunction with an application add-in called the FPGA Dynamic Probe
  
  
• Core-assisted approach accelerates debug of FPGA DDR II interfaces (Jun. 21, 2006)
  In this tutorial, a debug methodology is described and applied to a real FPGA-based DDR II high-speed memory controller debug example.
  
  
• Broadcast video infrastructure implementation using FPGAs (Jun. 07, 2006)
  The proliferation of high-definition television (HDTV) video content creation and the method of delivering these contents in a bandwidth-limited broadcast channel environment have driven new video compression standards and associated video image processin
  
  
• How to lower the cost of PCI Express adoption by using FPGAs (Apr. 26, 2006)
  This article shows how FPGAs are driving the adoption of PCI Express in the embedded market.
  
  
• How to build reliable FPGA memory interface controllers without writing your own RTL code! (Apr. 19, 2006)
  What if a designer could simply use a GUI to input the memory system parameters and generate RTL code for use in an FPGA without writing it from scratch?
  
  
• Combining FPGAs and DSPs to get the best performance (Apr. 18, 2006)
  How intelligent partitioning between DSPs and FPGAs will deliver the best combination of features and cost-effectiveness for such things as wireless basestation applications.
  
  
• FPGAs and Structured ASICs: Low-Risk SoC for the Masses (Apr. 13, 2006)
  This paper will explain how new ASSP ventures face challenges that can derail success of a product even before the first device is sold, including market entry barriers such as time to market pressures, limited human and financial resources, and increased