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Revolutionizing Chip Design with AI-Driven EDA |
Sep. 02, 2024 |
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Synopsys 3DIO Solution for Multi-Die Integration (2.5D/3D) |
May. 02, 2024 |
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Maximizing Performance & Reliability for Flash Applications with Synopsys xSPI Solution |
Mar. 04, 2024 |
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Three Major Inflection Points for Sourcing Bluetooth Intellectual Property |
Jan. 22, 2024 |
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Leveraging IBIS-AMI Models to Optimize PCIe 6.0 Designs |
Jun. 15, 2023 |
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Achieving Your Low Power Goals with Synopsys Ultra Low Leakage IO |
May. 08, 2023 |
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What Designers Need to Know About USB Low-Power States |
Jan. 09, 2023 |
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Radiation Tolerance is not just for Rocket Scientists: Mitigating Digital Logic Soft Errors in the Terrestrial Environment |
Nov. 28, 2022 |
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How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power |
Nov. 21, 2022 |
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Multi-Die SoCs Gaining Strength with Introduction of UCIe |
Aug. 29, 2022 |
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Automotive electronics revolution requires faster, smarter interfaces |
May. 19, 2022 |
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Easing PCIe 6.0 Integration from Design to Implementation |
Mar. 01, 2022 |
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AI, and the Real Capacity Crisis in Chip Design |
Feb. 24, 2022 |
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Calibrate and Configure your Power Management IC with NVM IP |
Feb. 21, 2022 |
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Why 400G/800G and Beyond Ethernet for High-Performance Computing Systems |
Oct. 12, 2021 |
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USB 3.2: A USB Type-C Challenge for SoC Designers |
Jan. 26, 2021 |
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Lower Process Nodes Drive Timing Signoff Software Evolution |
Dec. 29, 2020 |
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The Growing Market for Specialized Artificial Intelligence IP in SoCs |
Nov. 26, 2020 |
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Avoid HPC Data Traffic Jams with High-Speed Interface IP |
Nov. 04, 2020 |
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Meeting Increasing Performance Requirements in Embedded Applications with Scalable Multicore Processors |
Aug. 24, 2020 |
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Testing Embedded MRAM IP for SoCs |
Mar. 02, 2020 |
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Choosing the Right IP for Die-to-Die Connectivity |
Feb. 03, 2020 |
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Securing Smart Connected Homes with OTP NVM |
Jan. 06, 2020 |
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Configure, Confirm, Ship: Build Secure Processor-Based Systems with Faster Time-to-Market |
Jul. 29, 2019 |
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Integrated ADAS Domain Controller SoCs with ISO 26262 Certified IP |
Apr. 22, 2019 |
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Which DDR SDRAM Memory to Use and When |
Mar. 18, 2019 |
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Right-Sizing Your Cryptographic Processing Solution |
Mar. 04, 2019 |
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Achieving Low power with Active Clock Gating for IoT in IPs |
Jan. 15, 2018 |
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Modular Design Of Level-2 Cache For Flexible IP Configuration |
Dec. 11, 2017 |
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Optimizing Designs Through System Simulation |
Dec. 07, 2017 |
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Combining USB Type-C and DisplayPort support in portable implementations |
Oct. 09, 2017 |
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Reduce Time to Market for FPGA-Based Communication and Datacenter Applications |
Sep. 14, 2017 |
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Context Based Clock Gating Technique For Low Power Designs of IoT Applications - A DesignWare IP Case Study |
Jul. 03, 2017 |
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Achieving FPGA Design Performance Quickly |
Jun. 26, 2017 |
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FPGA-Based Functional Safety for Industrial Applications |
May. 10, 2017 |
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Improving Inter Integrated Circuits - From Sensor Hubs to Platform Management Solutions |
May. 01, 2017 |
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Achieving High Performance Non-Volatile Memory Access Through "Execute-In-Place" Feature |
Apr. 24, 2017 |
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Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP |
Apr. 17, 2017 |
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Achieving FPGA Design Performance Quickly |
Feb. 09, 2017 |
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Configurable Microprocessor for Life Essential Devices |
Feb. 06, 2017 |
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Functional Safety and the FPGA World |
Oct. 25, 2016 |
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Automotive Is the New Black |
Aug. 12, 2016 |
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Faster and Fewer Patterns with Breakthrough ATPG to the Rescue |
Aug. 11, 2016 |
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Choosing a mobile-storage interface: eMMC or UFS |
Jul. 26, 2016 |
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Versatile FPGA IP Handing, Creation, and Packaging |
Jul. 22, 2016 |
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FPGA constraints for the modern world: Product how-to |
Jul. 08, 2016 |
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Foundation IP for 7nm FinFETs: Design and Implementation |
Apr. 18, 2016 |
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FPGA Debug in the Modern World |
Apr. 12, 2016 |
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Designing an Efficient DSP Solution: Choosing the Right Processor and Software Development Toolchain |
Feb. 22, 2016 |
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Delivering High Quality Analog Video Signals With Optimized Video DACs |
Feb. 15, 2016 |
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Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures |
Feb. 08, 2016 |
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Don't over-constrain in formal property verification (FPV) flows |
Feb. 08, 2016 |
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Addressing Three Critical Challenges of USB Type-C Implementation |
Feb. 01, 2016 |
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True Random Number Generators for Truly Secure Systems |
Jan. 18, 2016 |
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FPGA Design: Faster Runtimes & Increased Productivity |
Jan. 14, 2016 |
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USB Type-C: Is it all just Hype-C for embedded designers? |
Dec. 14, 2015 |
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Design, Test & Repair Methodology for FinFET-Based Memories |
Nov. 30, 2015 |
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Safety in SoCs: Accelerating the Road to ISO 26262 Certification for the ARC EM Processor |
Nov. 23, 2015 |
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Smart way to memory controller verification: Synopsys Memory VIP |
Nov. 02, 2015 |
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Anatomy of the HDMI IP Certification Flow |
Sep. 07, 2015 |
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