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Virage Logic

Title Sign Up for SoC News Alert	Publication


Selecting the right Nonvolatile Memory IP: Applications and Alternatives	May. 25, 2010

Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2	Aug. 31, 2009

IP/foundry ecosystem facilitates 45-nm process design	Jul. 27, 2007

Protecting IP in a Modern Design Flow	Mar. 05, 2007

Under the Hood of Library IP (by Brani Buric and Mike Colwell, Virage Logic)	Oct. 10, 2003

Virage pulls back the covers to detail platforms	May. 05, 2003

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