8-stage superscalar processor that supports ISO 26262 ASIL-D level functional safety for automotive applications
40G UCIe PHY for high-density advanced packages
High speed 3.3V I/0 Library with 8kV ESD protection in TPSCo 65nm technology
Low jitter, low-power clock-deskew PLL operating from 6GHz to 9.5GHz on GF 22nm FDX
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Joachim Kunkel Joins Arteris Board of Directors
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An Introduction to Direct RF Sampling in a World Evolving Towards Chiplets - Part 1
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Optimizing Analog Layouts: Techniques for Effective Layout Matching
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