Title Sign Up for SoC News Alert  |
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PLI based applications |
Dec. 07, 2015 |
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How to Ensure a Bug Free BootROM? |
Nov. 30, 2015 |
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Efficient logic optimization utilizing complementary behavior of CMOS gates |
Nov. 23, 2015 |
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Analog IP verification guidelines |
Nov. 19, 2015 |
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Scan Lockup Latches - Significant Role in Congestion |
Oct. 19, 2015 |
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Best design practices for DFT |
Oct. 15, 2015 |
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Challenges in verifying PCI Express in complex SoCs |
Oct. 12, 2015 |
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Timing closure in multi-level partitioned SoCs |
Oct. 08, 2015 |
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Design Rule Violation fixing in timing closure |
Oct. 05, 2015 |
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Reducing IC power consumption: Low-power design techniques |
Sep. 25, 2015 |
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LBIST - A technique for infield safety |
Sep. 21, 2015 |
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All you need to know about MIPI D-PHY RX |
Sep. 16, 2015 |
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Timing Aware Redundant Buffer Removal |
Sep. 14, 2015 |
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An Automated Flow for Reset Connectivity Checks in Complex SoCs having Multiple Power Domains |
Sep. 07, 2015 |
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Method for Booting ARM Based Multi-Core SoCs |
Aug. 31, 2015 |
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Clock Gating Checks on Multiplexers |
Aug. 24, 2015 |
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PLL Subsystem architectures for SoC design |
Aug. 24, 2015 |
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Motion Picture: a Reality on Emulation Platform |
Aug. 17, 2015 |
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Estimate power at RTL to identify problems early |
Aug. 10, 2015 |
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Security in vehicular systems |
Aug. 03, 2015 |
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Lockup Elements - The Timing Perspective |
Aug. 03, 2015 |
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Accurate and Efficient Power estimation Flow For Complex SoCs |
Jul. 27, 2015 |
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DDR simulation strategy catches bugs early |
Jul. 22, 2015 |
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Device Malfunction due to Faulty Digital circuit along with suggested Remedies |
Jul. 20, 2015 |
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Debugging LBIST safe-stating issues |
Jul. 13, 2015 |
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Configurable Asynchronous Set/Reset Flip-Flop for Post-Silicon ECOs |
Jul. 06, 2015 |
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Reset connectivity checks in complex low power architectures |
Jul. 06, 2015 |
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Memory fault models and testing |
Jun. 30, 2015 |
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Building Process For the C/C++ Program on Complex SoCs |
Jun. 29, 2015 |
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Reducing chip IR drop in backward-compatible power bar-limited LQFP SoCs |
Jun. 24, 2015 |
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Efficient methodology for design and verification of Memory ECC error management logic in safety critical SoCs |
Jun. 22, 2015 |
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Sequential architecture for absolutely NO hold requirement in the Shift path |
Jun. 22, 2015 |
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Methodology improves SoC power grids |
Jun. 17, 2015 |
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Delay Characterization for Sequential Cell |
Jun. 15, 2015 |
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Documentation First! unifies design flow |
Jun. 09, 2015 |
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An efficient way of loading data packets and checking data integrity of memories in SoC verification environment |
Jun. 08, 2015 |
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Structural netlist efficiently verifies analog IP |
Jun. 05, 2015 |
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Robust Low power Architecture verification Strategy |
Jun. 01, 2015 |
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High Density - Low power Flip-Flop |
Jun. 01, 2015 |
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Verification of various SoC features through SV assertions |
May. 25, 2015 |
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Safety intended Re-configurable Automotive microcontroller with reduced boot-up time |
May. 21, 2015 |
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Verification Challenges of High Speed Interfaces |
May. 18, 2015 |
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Automotive Security & Internet of Tomorrow (IoT) |
May. 13, 2015 |
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Risks and Precautions to take care while using On-Chip temperature sensors in Safety critical automotive applications |
May. 11, 2015 |
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Efficient methodology for verification of Dynamic Frequency Scaling of clocks in SoC |
May. 04, 2015 |
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Method to minimize switching activity in digital data transfer protocols |
Apr. 27, 2015 |
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Method for Library Analysis Automation |
Apr. 20, 2015 |
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When Developing New Silicon IP, Is First Pass Success Possible? |
Apr. 02, 2015 |
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Analysis of RDC Paths for a million gate SoC |
Mar. 30, 2015 |
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Dynamically controlled logic gate design for all power modes |
Mar. 23, 2015 |
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Security needs more than checklist compliance |
Mar. 12, 2015 |
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Queue Based Interrupt Service Protocol for Error Detection |
Mar. 09, 2015 |
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Dual edge sequential architecture capable of eliminating complete hold requirement from the test path |
Mar. 02, 2015 |
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Buffer design for reducing Hold violations & IR drop |
Feb. 17, 2015 |
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Efficient Buffer design for Hold fixing |
Feb. 02, 2015 |
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Pitfalls for Logical Equivalence Check |
Jan. 19, 2015 |
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A High Density, High Performance, Low Power Level Shifter |
Jan. 05, 2015 |
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SoC clock monitoring issues: Scenarios and root cause analysis |
Dec. 19, 2014 |
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Techniques for CDC Verification of an SoC |
Dec. 08, 2014 |
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Creating core independent stimulus in a multi-core SoC verification environment |
Nov. 24, 2014 |
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