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Resilience in Space: Designing Radiation-Tolerant Systems |
Oct. 22, 2021 |
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Realizing 5G New Radio massive MIMO systems |
Jan. 15, 2018 |
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Programmable Logic Holds the Key to Addressing Device Obsolescence |
Dec. 19, 2017 |
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Handling Asynchronous Clock Groups in SDC |
Nov. 18, 2013 |
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All eyes on Zynq SoC for smarter vision |
May. 17, 2013 |
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FPGAs offer cost-effective, flexible solutions for remote radio heads |
Apr. 19, 2013 |
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How a MicroBlaze can peaceably coexist with the Zynq SoC |
Mar. 28, 2013 |
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Developing FPGA applications for Edition 2 of the IEC 61508 Safety Standard |
Jan. 28, 2013 |
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Small Cells - How fast and how many? |
Oct. 23, 2012 |
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Optimizing FPGAs for power: A full-frontal attack |
Jun. 19, 2012 |
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Inside the Xilinx Kintex-7 FPGA: A closer look at the first FPGA to use HKMG technology |
Apr. 06, 2012 |
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2.5D ICs are more than a stepping stone to 3D ICs |
Mar. 28, 2012 |
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2.5-D will be a market of its own |
Mar. 01, 2012 |
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How to build a self-checking testbench |
Feb. 27, 2012 |
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PowerSoC solves switch-mode DCDC noise and space issues |
Feb. 06, 2012 |
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Single event effects (SEEs) in FPGAs, ASICs, and processors, part I: impact and analysis |
Dec. 15, 2011 |
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Using FPGAs to solve challenges in industrial applications |
Nov. 23, 2011 |
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Creating the Xilinx Zynq-7000 Extensible Processing Platform |
Oct. 18, 2011 |
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How do I reset my FPGA? |
Aug. 11, 2011 |
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Zynq-7000 EPP sets stage for new era of innovations |
Jun. 20, 2011 |
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Optimize data flow video apps by tightly coupling ARM-based CPUs to FPGA fabrics |
May. 12, 2011 |
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Repeatable results with design preservation |
Jun. 10, 2010 |
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Xilinx Virtex-6 FPGA User Guide Lite |
Aug. 06, 2009 |
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Implementing LTE on FPGAs |
Feb. 09, 2009 |
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Solving FPGA I/O pin assignment challenges |
Nov. 20, 2008 |
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Using FPGAs to improve your wireless subsystem's performance |
Aug. 25, 2008 |
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How to simplify power design development and evaluation for FPGA-based systems |
Jul. 10, 2008 |
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Xilinx responds to Altera's FPGA benchmarks |
Jun. 02, 2008 |
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Tips on using CPLDs to reduce system processor power consumption |
May. 27, 2008 |
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How to design portable handsets using CPLDs |
May. 22, 2008 |
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Strategies for minimizing Xilinx implementation tool runtimes |
Mar. 24, 2008 |
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Designing FPGA Based Reliable Systems Using Virtex-5 System Monitor |
Mar. 10, 2008 |
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FPGA-Based Prototyping - "Productivity to Burn" |
Jan. 31, 2008 |
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FPGA design and verification using Simulink |
Jan. 14, 2008 |
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Designing DDR3 SDRAM controllers with today's FPGAs |
Dec. 13, 2007 |
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Generate FPGA designs from M-code |
Nov. 15, 2007 |
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Cost-effective two-dimensional rank-order filters on FPGAs |
Sep. 20, 2007 |
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How to support multiple SD devices using CPLDs |
Aug. 23, 2007 |
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Floating- to fixed-point MATLAB algorithm conversion for FPGAs |
Jun. 04, 2007 |
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A tutorial on tools, techniques, and methodology to improve FPGA designer productivity |
Apr. 26, 2007 |
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Triple play - How FPGAs can tackle the challenges of network security |
Mar. 15, 2007 |
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How to map the H.264/AVC video standard onto an FPGA fabric |
Mar. 05, 2007 |
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How to improve design-level security with low-cost non-volatile FPGAs |
Mar. 01, 2007 |
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Designing with Virtex-5 Embedded Tri-Mode Ethernet MACs |
Feb. 05, 2007 |
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How to design 65nm FPGA DDR2 memory interfaces for signal integrity |
Jan. 25, 2007 |
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How to maximize FPGA performance |
Jan. 15, 2007 |
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Tutorial: Floating-point arithmetic on FPGAs |
Dec. 13, 2006 |
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How to use CPLDs to implement a QWERTY keypad |
Dec. 04, 2006 |
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How to get more performance in 65 nm FPGA designs |
Nov. 08, 2006 |
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How to tackle serial backplane challenges with high-performance FPGA designs |
Oct. 26, 2006 |
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How to design FPGA-based advanced PCI Express endpoint solutions |
Oct. 19, 2006 |
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Implementing matrix inversions in fixed-point hardware |
Oct. 12, 2006 |
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How to use FPGAs to implement MOST in automobiles |
Oct. 09, 2006 |
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How to use CPLDs to manage average power consumption in portable applications |
Sep. 28, 2006 |
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How to reduce power using I/O gating (CPLDs) versus sleep modes (FPGAs) |
Sep. 21, 2006 |
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Rapid Prototyping and Verification of MIMO Systems |
Aug. 03, 2006 |
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Meeting signal integrity requirements in FPGAs with high-end memory interfaces |
Jan. 18, 2006 |
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