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Optimizing Electronics Design With AI Co-Pilots |
Nov. 28, 2023 |
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The Network Switch: Unsung Hero of the Hyper-Scale Data Center |
Oct. 07, 2021 |
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EDA in the Cloud Will be Key to Rapid Innovative SoC Design |
Aug. 23, 2021 |
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Agile Verification for SoC Design |
Jun. 07, 2021 |
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AI Challenges for Next-Gen EDA |
May. 03, 2019 |
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EDA Finds a Common Framework for AI |
Apr. 29, 2019 |
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Safety Verification and Optimization of Automotive Ethernet Using Dedicated SoC FIT Rates |
Mar. 09, 2017 |
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A Look at New Open Standards to Improve Reliability and Redundancy of Automotive Ethernet |
Nov. 10, 2016 |
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Massively parallel frameworks for in-design verification |
Oct. 31, 2016 |
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What's in the Future for High-Speed SerDes? |
Jun. 16, 2016 |
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Securing the Most Important Goal of USB Type-C Technology: A Better User Experience |
Feb. 17, 2016 |
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How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity |
Jan. 21, 2016 |
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Designing High Performance Interposers with 3-port and 6-port S-parameters |
Oct. 19, 2015 |
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Testing PSRR with High-Frequency Ripple |
Oct. 01, 2015 |
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USB 3.1 Gen 2 Brings Higher Data Rates with Architecture Improvements |
Sep. 28, 2015 |
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Design Implications of USB Type-C |
May. 13, 2015 |
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IP and system design lower data centre power consumption |
Apr. 13, 2015 |
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Building a high-performance, low-power audio/voice subsystem |
Mar. 26, 2015 |
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Selecting an Optimized ADC for a Wireless AFE |
Mar. 23, 2015 |
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Choosing the right A/D converter architecture and IP to meet the latest high speed wireless standards |
Oct. 15, 2014 |
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Hybrid execution - the next step in the evolution of hardware-software co-development |
Jun. 09, 2014 |
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RTL synthesis requirements for advanced node designs |
Jan. 02, 2014 |
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Automotive System & Software Development Challenges - Part 1 |
Nov. 15, 2013 |
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Automotive System & Software Development Challenges - Part 2 |
Nov. 15, 2013 |
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Moving to SystemC TLM for design and verification of digital hardware |
May. 13, 2013 |
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Building Your UVM Verification Environment for Cache Coherent Interconnects |
Apr. 01, 2013 |
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Electrically-aware design improves analog/mixed-signal productivity |
Oct. 29, 2012 |
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Mixed-signal SOC verification using analog behavioral models |
Aug. 23, 2012 |
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Top 10 Tips for Success with Formal Analysis - Part 3 |
May. 14, 2012 |
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Hierarchical methods for power intent specification |
Apr. 30, 2012 |
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Building predictability into your low-power design flow |
Apr. 17, 2012 |
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Building a NAND flash controller with high-level synthesis |
Mar. 22, 2012 |
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Wide I/O driving 3-D with through-silicon vias |
Mar. 01, 2012 |
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Top 10 Tips for Success with Formal Analysis - Part 2 |
Jan. 31, 2012 |
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Top 10 Tips for Success with Formal Analysis - Part 1 |
Dec. 12, 2011 |
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3D-IC Design: The Challenges of 2.5D versus 3D |
Sep. 19, 2011 |
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3-D IC design: New possibilities for the wireless market |
Jun. 08, 2011 |
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Mixed-Signal = Analog + Digital, or is there more to it? |
Mar. 01, 2011 |
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Metric Driven Validation, Verification and Test of Embedded Software |
Nov. 08, 2010 |
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Reduce embedded SoC design cost & optimize IP integration |
Aug. 10, 2010 |
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Using unified modeling methods to reduce embedded hardware/software development |
May. 13, 2010 |
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Lowering test costs in the nanometer era |
Dec. 16, 2009 |
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Why Football Players are Like Verification Engineers |
Oct. 22, 2009 |
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Viewpoint: Low-power design brings chip, software together |
Dec. 22, 2008 |
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ESL handoff: closer than you think |
Jul. 08, 2008 |
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What floorplan information is needed for synthesis |
Apr. 24, 2008 |
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Power mode technologies verify today's SoCs |
Feb. 28, 2008 |
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Multi-language Functional Verification Coverage for Multi-site Projects |
Feb. 18, 2008 |
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Simplifying PLL Design |
Feb. 13, 2008 |
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Making Verification Methodology and Tool Decisions |
Aug. 06, 2007 |
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A system-level verification flow for EDA |
Mar. 19, 2007 |
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Methodology for protection and Licensing of HDL IP |
Mar. 06, 2006 |
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The Challenge of Keeping IP Usable |
Jun. 02, 2005 |
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