Title Sign Up for SoC News Alert  |
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Optimizing Analog Layouts: Techniques for Effective Layout Matching |
Aug. 26, 2024 |
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BCD Technology: A Unified Approach to Analog, Digital, and Power Design |
Aug. 05, 2024 |
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Understanding mmWave RADAR, its Principle & Applications |
Mar. 11, 2024 |
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Performance Evaluation of machine learning algorithms for cyber threat analysis SDN dataset |
Jan. 15, 2024 |
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Power analysis in 7nm Technology node |
Dec. 04, 2023 |
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Writing a modular Audio Post Processing DSP algorithm |
Oct. 30, 2023 |
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Understanding Timing Correlation Between Sign-off Tool and Circuit Simulation |
Oct. 09, 2023 |
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Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2) |
Sep. 25, 2023 |
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I2C Interface Timing Specifications and Constraints |
Sep. 11, 2023 |
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Understanding the Importance of Prerequisites in the VLSI Physical Design Stage |
Aug. 21, 2023 |
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How AI (Artificial Intelligence) Is Transforming the Aerospace Industry |
May. 29, 2023 |
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Floorplan Guidelines for Sub-Micron Technology Node for Networking Chips |
May. 01, 2023 |
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Fmax Margin/Value Improvement for Memory Block During ECO Stage |
Apr. 17, 2023 |
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IoT Security: Exploring Risks and Countermeasures Across Industries |
Mar. 13, 2023 |
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Synthesis Methodology & Netlist Qualification |
Aug. 15, 2022 |
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A Generic Solution to GPIO verification |
Aug. 01, 2022 |
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Implementing C model integration using DPI in SystemVerilog |
Jun. 27, 2022 |
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Understanding Interface Analog-to-Digital Converters (ADCs) with DataStorm DAQ FPGA |
May. 30, 2022 |
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Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution |
Mar. 21, 2022 |
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Crux of Custom Power & Special Net Routing |
Dec. 20, 2021 |
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Software Architecture for DO-160 Qualification of STM32H7 based systems |
Oct. 25, 2021 |
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Creating IP level test cases which can be reused at SoC level |
May. 24, 2021 |
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Verifying Dynamic Clock switching in Power-Critical SoCs |
Jan. 18, 2021 |
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Smart Wave Dump - A smart way to generate waveforms |
Jan. 04, 2021 |
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Congestion & Timing Optimization Techniques at 7nm Design |
Dec. 21, 2020 |
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Gathering Regression List for Structural Coverage Analysis |
Nov. 30, 2020 |
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Optimizing Floorplan for STA and Timing improvement in VLSI Design Flow |
Nov. 09, 2020 |
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Next Gen Scan Compression Technique to overcome Test challenges at Lower Technology Nodes (Part - I) |
Oct. 26, 2020 |
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VLSI Physical Design Methodology for ASIC Development with a Flavor of IP Hardening |
Oct. 19, 2020 |
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Reducing Debug time for Scan pattern using Parallel Strobe Data (PSD) Flow |
Sep. 21, 2020 |
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Optimization of Crosstalk Delta Delay on Clock Nets |
Aug. 24, 2020 |
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DDR IP Hardening - Overview & Advance Tips |
Jul. 27, 2020 |
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Scan Chains: PnR Outlook |
Jul. 20, 2020 |
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Antenna Effect in 16nm Technology Node |
Jun. 29, 2020 |
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Reduce ATPG Simulation Failure Debug Time by Understanding and Editing SPF |
May. 11, 2020 |
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Methodology to reduce Run Time of Timing/Functional Eco |
Apr. 27, 2020 |
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Embedded Software Unit Testing with Ceedling |
Apr. 14, 2020 |
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Shift Power Reduction Methods and Effectiveness for Testability in ASIC |
Mar. 16, 2020 |
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Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 2 |
Mar. 09, 2020 |
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Strategy To Fix Register-to-Register Timing For large Feedthrough Blocks Having Limited Internal Pipelines |
Mar. 05, 2020 |
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Layout versus Schematic (LVS) Debug |
Feb. 10, 2020 |
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Interface Timing Challenges and Solutions at Block Level |
Jan. 27, 2020 |
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Setup Margin Aware Quick Hold Fixing |
Jan. 13, 2020 |
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Understanding Shmoo Plots and Various Terminology of Testers |
Jan. 06, 2020 |
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Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 1 |
Dec. 09, 2019 |
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UVM RAL Model: Usage and Application |
Sep. 02, 2019 |
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Testing Of Repairable Embedded Memories in SoC: Approach and Challenges |
Jun. 17, 2019 |
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Area Overhead: GOH Control and Track |
May. 13, 2019 |
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Distorted Waveform Phenomena in 7nm Technology Node and its Impact on Signoff Timing Analysis |
May. 06, 2019 |
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System Verilog Macro: A Powerful Feature for Design Verification Projects |
Apr. 18, 2019 |
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Memory Testing - An Insight into Algorithms and Self Repair Mechanism |
Apr. 08, 2019 |
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Signoff Iteration Reduction Technique for Fixing Top Level Antenna |
Apr. 01, 2019 |
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A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology |
Mar. 25, 2019 |
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Reducing DFT Footprints: A Case in Consumer SoC |
Mar. 11, 2019 |
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Cost Reduction and Improved TTR with Shared Scan-in DFT CODEC |
Feb. 25, 2019 |
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A Guide on Logical Equivalence Checking - Flow, Challenges, and Benefits |
Feb. 11, 2019 |
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Designing an Effective Traffic Management System Through Vehicle Classification and Counting Techniques |
Nov. 29, 2018 |
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System Verilog Assertions Simplified |
Oct. 22, 2018 |
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Implementing Parallel Processing and Fine Control in Design Verification |
Sep. 17, 2018 |
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Usage of Multibit Flip-Flop and its Challenges in ASIC Physical Design |
Jul. 23, 2018 |
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