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IP / SOC Products Articles

• What is JESD204B? Quick summary of the standard (Feb. 12, 2025)
  The JESD204B Standard enables the establishment of high-speed serial links between a Controller and ADC and DAC converters with Deterministic Latency. JESD204B was first published in July 2011 and was the first JESD204 standard version to describe the deterministic latency mechanism.
  
  
• Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World (Feb. 10, 2025)
  Quantum computing advances are exciting, but they’re also a looming threat to securing ICs, driving the need for Post-Quantum Cryptography (PQC). Learn about PQC, how it’s being implemented, and the legislation involved.
  
  
• Understanding why power management IP is so important (Feb. 05, 2025)
  Power management IP is indispensable in modern chip design, especially for battery applications where power is constrained and for high-power applications where thermal efficiency is vital. Power management IPs are specialized blocks or circuits that help to control the power consumption, voltage levels and energy efficiency of a system.
  
  
• Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design (Jan. 29, 2025)
  As the semiconductor industry pushes the boundaries of innovation, modern system-on-chip (SoC) designs are growing exponentially in size and complexity. With hundreds of IP blocks and thousands of interconnects to manage, the challenges of maintaining performance, maximizing efficiencies, and meeting time-to-market demands are more significant than ever.
  
  
• SoC design: What's next for NoCs? (Jan. 27, 2025)
  SoC designers face rapid expansion in architecture, time-to-market pressures, scarcity of expertise, suboptimal utilization of resources, and disparate toolchains.
  
  
• Synopsys Foundation IP Enabling Low-Power AI Processors (Jan. 23, 2025)
  The data center industry is attempting to alleviate the power demand by moving away from traditional air-cooled systems and turning to more expensive but highly effective liquid cooling solutions. However, relying solely on advancements in external cooling is not enough. To manage these increasing power demands, AI hardware developers must also innovate within the system design itself, exploring more comprehensive avenues for power optimization.
  
  
• Automotive Ethernet Security Using MACsec (Jan. 20, 2025)
  The traditional automotive architecture, which assigns a dedicated Electronic Control Unit (ECU) to each vehicle function and connects them through protocols like CAN, LIN, and FlexRay, can no longer support modern vehicles’ needs.
  
  
• What is JESD204C? A quick glance at the standard (Jan. 09, 2025)
  The JESD204C standard enables establishing high-speed serial links between a Controller and ADC and DAC converters. JESD204C was first published in December of 2017 as an iteration of the JESD204B Standard published six years prior in July 2011.
  
  
• Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology (Jan. 06, 2025)
  This white paper explores the integration of advanced PVT sensors into DVFS frameworks to overcome these limitations. Building on research innovations in energy-efficient computing, the paper demonstrates how Innosilicon’s PVT sensor provides a reliable and scalable solution to address process variability, voltage scaling, and thermal management.
  
  
• Quantum Readiness Considerations for Suppliers and Manufacturers (Dec. 16, 2024)
  The issue of quantum readiness is gaining momentum, as suppliers and manufacturers realize the importance of the transition to post-quantum cryptography.
  
  
• A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR) (Dec. 16, 2024)
  TMR is not a new idea in the world of ASIC design. It was published as far back as 1962 in the IBM Journal of Research and Development. However, it has become an essential design solution for ASIC chips sent into space, a vast environment filled with radiation.
  
  
• The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification (Dec. 02, 2024)
  Building on the success of achieving PSA Certified™ Level 2 Ready through the integration of PUFcc with Arm’s CPU, Corstone platform, and TF-M, PUFsecurity and Arm move forward to the next level and successfully attain SESIP and PSA Certified™ Level 3 RoT Component certification for PUFsecurity’s Crypto Coprocessor IP, PUFcc.
  
  
• Last-Time Buy Notifications For Your ASICs? How To Make the Most of It (Nov. 12, 2024)
  This article explores the history of the 600 nm process, the reasons behind its phase-out, and what the industry has to look forward to as smaller, more efficient chips become the new standard.
  
  
• CANsec: Security for the Third Generation of the CAN Bus (Oct. 28, 2024)
  CANsec is a resource-efficient solution for securing the CAN bus against the most common cyber security threats on software-defined vehicles. Here we show that the encryption and authentication of CAN XL frames are possible without latencies or loss of bandwidth.
  
  
• Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning (Oct. 23, 2024)
  A new trend is emerging in the design of high-end, multi-billion-transistor system-on-chip (SoC) devices. Referred to as “NoC tiling,” this evolutionary approach uses proven, robust network-on-chip (NoC) technology to facilitate scaling, condense design time, speed testing, and reduce risk.
  
  
• A new era for embedded memory (Oct. 17, 2024)
  While flash memory is still the most popular non- volatile memory (NVM), several applications are beginning to adopt other types of embedded NVM technology, both because embedded flash can’t feasibly scale beyond 28nm and because of cost, power, and performance advantages.
  
  
• Electronic musical instruments design: what's inside counts (Oct. 04, 2024)
  Digital electronics has profoundly changed musical instrument design. From toy keyboards to performance-grade pianos, synthesizers, and drum sets, to name a few, instruments that once would have been finely crafted wood and metal can today find their voices in CPUs, memory, and data converters.
  
  
• An Introduction to Direct RF Sampling in a World Evolving Towards Chiplets - Part 1 (Sep. 02, 2024)
  This paper focuses on how direct RF sampling architecture has proved to be a felicitous approach for RF data conversion. The progress in converter technology has made it possible to increase the sampling rates and support very large bandwidth and multiple operating RF bands.
  
  
• How to cost-efficiently add Ethernet switching to industrial devices (Aug. 28, 2024)
  This post explores critical considerations and solutions for implementing Ethernet switches tailored to industrial applications, emphasizing required features and cost-effectiveness.
  
  
• Why Interlaken is a great choice for architecting chip to chip communications in AI chips (Aug. 21, 2024)
  The Interlaken protocol is an advanced interconnect technology that effectively addresses the architecture and design requirements of AI chips. It provides high bandwidth through multi-gigabit-per-second lanes, facilitating the handling of large data volumes and sustaining high computational throughput.
  
  
• Key considerations and challenges when choosing LDOs (Aug. 12, 2024)
  The vast array of on-chip LDO options and characteristics can make the selection process complex.
  
  
• NoCs and the transition to multi-die systems using chiplets (Aug. 05, 2024)
  Monolithic dies have long been used in integrated circuit (IC) design, offering a compact and efficient solution for building application-specific integrated circuits (ASICs), application-specific standard parts (ASSPs) and systems-on-chip (SoCs).
  
  
• How to Turbo Charge Your SoC's CPU(s) (Jul. 29, 2024)
  It’s no surprise that the creators of system-on-chip (SoC) devices wish to squeeze the maximum performance out of their systems. One way to do this is to use the highest-performing intellectual property (IP) cores available, including Central Processing Unit (CPU) cores.
  
  
• Rising respins and need for re-evaluation of chip design strategies (Jul. 25, 2024)
  As a result of design complexity and market competition, innovative chip development strategies have become essential for expedited market entry and revenue growth. Tapping into these technological advances is a strategic imperative to secure market leadership.
  
  
• Simplifying analog and mixed-signal design integration (Jul. 24, 2024)
  Analog and mixed-signal design are an essential part of modern electronics. At Agile Analog, we often hear that digital design engineers find integrating analog components can be a daunting task. So, what are the main differences between digital and analog design, and how can the analog and mixed-signal design integration process be simplified?
  
  
• AI-driven SRAM demand needs integrated repair and security (Jul. 22, 2024)
  Increasing popularity of AI applications and DPU architecture has led to growing demand for higher SRAM densities, in turn placing challenges on SRAM yield and reliability.
  
  
• Understanding the contenders for the Flash memory crown (Jul. 11, 2024)
  Embedded flash memory is reaching its limits as technology nodes for embedded applications shrink below 28nm
  
  
• Select the Right Microcontroller IP for Your High-Integrity SoCs (Jul. 08, 2024)
  There may be a seemingly unlimited array of microcontrollers for consideration, but how do you select the right one when developing high-integrity SoCs that meet all functional-safety requirements?
  
  
• Optimal OTP for Advanced Node and Emerging Applications (Jul. 03, 2024)
  While leading foundries keep pushing Moore’s law to the limit of physics, embedded non-volatile memory (eNVM) is becoming a game-changer in designing advanced integrated chips.
  
  
• Adding Cache to IPs and SoCs (Jul. 01, 2024)
  Integrating cache memory into SoCs and IP blocks improves their performance and efficiency. This article highlights technologies and strategies to address challenges like cache coherency and power consumption.