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IP / SOC Products Articles

• Quantum Readiness Considerations for Suppliers and Manufacturers (Dec. 16, 2024)
  The issue of quantum readiness is gaining momentum, as suppliers and manufacturers realize the importance of the transition to post-quantum cryptography.
  
  
• A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR) (Dec. 16, 2024)
  TMR is not a new idea in the world of ASIC design. It was published as far back as 1962 in the IBM Journal of Research and Development. However, it has become an essential design solution for ASIC chips sent into space, a vast environment filled with radiation.
  
  
• The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification (Dec. 02, 2024)
  Building on the success of achieving PSA Certified™ Level 2 Ready through the integration of PUFcc with Arm’s CPU, Corstone platform, and TF-M, PUFsecurity and Arm move forward to the next level and successfully attain SESIP and PSA Certified™ Level 3 RoT Component certification for PUFsecurity’s Crypto Coprocessor IP, PUFcc.
  
  
• Last-Time Buy Notifications For Your ASICs? How To Make the Most of It (Nov. 12, 2024)
  This article explores the history of the 600 nm process, the reasons behind its phase-out, and what the industry has to look forward to as smaller, more efficient chips become the new standard.
  
  
• CANsec: Security for the Third Generation of the CAN Bus (Oct. 28, 2024)
  CANsec is a resource-efficient solution for securing the CAN bus against the most common cyber security threats on software-defined vehicles. Here we show that the encryption and authentication of CAN XL frames are possible without latencies or loss of bandwidth.
  
  
• Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning (Oct. 23, 2024)
  A new trend is emerging in the design of high-end, multi-billion-transistor system-on-chip (SoC) devices. Referred to as “NoC tiling,” this evolutionary approach uses proven, robust network-on-chip (NoC) technology to facilitate scaling, condense design time, speed testing, and reduce risk.
  
  
• A new era for embedded memory (Oct. 17, 2024)
  While flash memory is still the most popular non- volatile memory (NVM), several applications are beginning to adopt other types of embedded NVM technology, both because embedded flash can’t feasibly scale beyond 28nm and because of cost, power, and performance advantages.
  
  
• Electronic musical instruments design: what's inside counts (Oct. 04, 2024)
  Digital electronics has profoundly changed musical instrument design. From toy keyboards to performance-grade pianos, synthesizers, and drum sets, to name a few, instruments that once would have been finely crafted wood and metal can today find their voices in CPUs, memory, and data converters.
  
  
• An Introduction to Direct RF Sampling in a World Evolving Towards Chiplets - Part 1 (Sep. 02, 2024)
  This paper focuses on how direct RF sampling architecture has proved to be a felicitous approach for RF data conversion. The progress in converter technology has made it possible to increase the sampling rates and support very large bandwidth and multiple operating RF bands.
  
  
• How to cost-efficiently add Ethernet switching to industrial devices (Aug. 28, 2024)
  This post explores critical considerations and solutions for implementing Ethernet switches tailored to industrial applications, emphasizing required features and cost-effectiveness.
  
  
• Why Interlaken is a great choice for architecting chip to chip communications in AI chips (Aug. 21, 2024)
  The Interlaken protocol is an advanced interconnect technology that effectively addresses the architecture and design requirements of AI chips. It provides high bandwidth through multi-gigabit-per-second lanes, facilitating the handling of large data volumes and sustaining high computational throughput.
  
  
• Key considerations and challenges when choosing LDOs (Aug. 12, 2024)
  The vast array of on-chip LDO options and characteristics can make the selection process complex.
  
  
• NoCs and the transition to multi-die systems using chiplets (Aug. 05, 2024)
  Monolithic dies have long been used in integrated circuit (IC) design, offering a compact and efficient solution for building application-specific integrated circuits (ASICs), application-specific standard parts (ASSPs) and systems-on-chip (SoCs).
  
  
• How to Turbo Charge Your SoC's CPU(s) (Jul. 29, 2024)
  It’s no surprise that the creators of system-on-chip (SoC) devices wish to squeeze the maximum performance out of their systems. One way to do this is to use the highest-performing intellectual property (IP) cores available, including Central Processing Unit (CPU) cores.
  
  
• Rising respins and need for re-evaluation of chip design strategies (Jul. 25, 2024)
  As a result of design complexity and market competition, innovative chip development strategies have become essential for expedited market entry and revenue growth. Tapping into these technological advances is a strategic imperative to secure market leadership.
  
  
• Simplifying analog and mixed-signal design integration (Jul. 24, 2024)
  Analog and mixed-signal design are an essential part of modern electronics. At Agile Analog, we often hear that digital design engineers find integrating analog components can be a daunting task. So, what are the main differences between digital and analog design, and how can the analog and mixed-signal design integration process be simplified?
  
  
• AI-driven SRAM demand needs integrated repair and security (Jul. 22, 2024)
  Increasing popularity of AI applications and DPU architecture has led to growing demand for higher SRAM densities, in turn placing challenges on SRAM yield and reliability.
  
  
• Understanding the contenders for the Flash memory crown (Jul. 11, 2024)
  Embedded flash memory is reaching its limits as technology nodes for embedded applications shrink below 28nm
  
  
• Select the Right Microcontroller IP for Your High-Integrity SoCs (Jul. 08, 2024)
  There may be a seemingly unlimited array of microcontrollers for consideration, but how do you select the right one when developing high-integrity SoCs that meet all functional-safety requirements?
  
  
• Optimal OTP for Advanced Node and Emerging Applications (Jul. 03, 2024)
  While leading foundries keep pushing Moore’s law to the limit of physics, embedded non-volatile memory (eNVM) is becoming a game-changer in designing advanced integrated chips.
  
  
• Adding Cache to IPs and SoCs (Jul. 01, 2024)
  Integrating cache memory into SoCs and IP blocks improves their performance and efficiency. This article highlights technologies and strategies to address challenges like cache coherency and power consumption.
  
  
• Creating SoC Designs Better and Faster With Integration Automation (Jun. 20, 2024)
  A modern high-end system-on-chip (SoC) design can be extremely large and enormously complex, employing thousands of intellectual property (IP) blocks. Most of these IPs will be sourced from trusted third-party vendors. These will typically be augmented by one or more internally-developed IPs to provide the secret sauce that will distinguish this SoC from its competitors.
  
  
• New Developments in MIPI's High-Speed Automotive Sensor Connectivity Framework (Jun. 18, 2024)
  Higher link speeds, security and a compliance program have been added to the MIPI Automotive SerDes Solutions framework.
  
  
• System-on-chip (SoC) design is all about IP management (Jun. 13, 2024)
  For most system-on-chip (SoC) designs, the most critical task is not RTL coding or even creating the chip architecture. Today, SoCs are designed primarily by assembling various silicon intellectual property (IP) blocks from multiple vendors. This makes managing silicon IP the dominant task in the design process.
  
  
• Speeding Derivative SoC Designs With Networks-on-Chips (Jun. 10, 2024)
  With the help of a case study, we examine how adopting NoC technology can significantly improve the process of updating existing chip designs.
  
  
• Procrastination Is All You Need: Exponent Indexed Accumulators for Floating Point, Posits and Logarithmic Numbers (Jun. 03, 2024)
  This paper discusses a simple and effective method for the summation of long sequences of floating point numbers. The method comprises two phases: an accumulation phase where the mantissas of the floating point numbers are added to accumulators indexed by the exponents and a reconstruction phase where the actual summation result is finalised.
  
  
• Temperature Sensors for ASICs (May. 24, 2024)
  A system’s operation hinges on the accuracy of an embedded temperature sensor‘s measurements. Therefore, choosing the correct integrated temperature sensor IP for your device is critical to your successful hardware designs.
  
  
• How control electronics can help scale quantum computers (May. 23, 2024)
  Quantum computing, with its potential to tackle problems way beyond the capabilities of standard computers, has ignited a global scientific and technological race.
  
  
• Why verification matters in network-on-chip (NoC) design (May. 21, 2024)
  In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that ensure our NoC designs are robust, efficient, and ready to meet the challenges of modern computing environments.
  
  
• Functional Safety for Control and Status Registers (May. 20, 2024)
  How to navigate the complexities of building functional safety into SoC design, including managing IP blocks, CSRs, and adhering to standards like ISO 26262.