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IP / SOC Products Articles

• Addressing SRAM Verification Challenges (Jun. 26, 2017)
  Verification is an integral part of any integrated circuit development process. The verification process must establish that the design meets its specified yield and performance criteria over the full range of operating conditions before tape-out sign-off. The process generally involves taking abstractions of the design in appropriate forms, for example post-layout extracted netlists, and running simulations to validate the design performance. The verification process must address many different aspects of yield and performance, so several different types of design abstraction and simulation tooling may be required to complete the process. In the case of SRAM this is particularly true.
  
  
• Introduction to Low Dropout (LDO) Linear Voltage Regulators (Jun. 15, 2017)
  Linear voltage regulators are key components in any power-management system that requires a stable and ripple-free power supply. A subset of linear voltage regulators is a class of circuits known as low dropout (LDO) regulators. This paper explains the fundamentals of LDOs and introduces Vidatronic’s LDO technology which solves many of the known shortcomings of LDO circuits.
  
  
• Communication Processors March on But 5G Demands Much More (Jun. 12, 2017)
  Development is well underway on Gigabit LTE cellular communications systems that promise an order of magnitude increase in data transfer rates and 5G is close behind. Small cell access nodes will form an essential part of both systems but new communications processors are needed to make these a reality.
  
  
• Ultra HD H.264 Video Codec IP solution on Zynq FPGA (May. 22, 2017)
  Numerous industries in broadcast, cable, videoconferencing and consumer electronics space are using H.264 as the video codec of choice for their products and services. The H.264/AVC video coding standard achieves a significant improvement in coding efficiency with increased computational complexity relative to former standards.
  
  
• USB Type-C and power delivery 101 - Power delivery protocol (May. 15, 2017)
  As described in the first part of this two-part series, USB Type-C is the newly introduced and powerful interconnect standard for USB. When paired with the new Power Delivery (PD) specification, Type-C offers enhancements to the existing USB 3.1 interconnect that lower the cost and simplify the implementation of power delivery over USB. In this article, we describe the USB Type-C power delivery protocol.
  
  
• USB Type-C and power delivery 101 - Ports and connections (May. 08, 2017)
  In this two part series, we describe power delivery with USB Type-C, starting with ports and connectors in this article, followed by the power delivery protocol in part two.
  
  
• Improving Inter Integrated Circuits - From Sensor Hubs to Platform Management Solutions (May. 01, 2017)
  This paper attempts to redefine these existing system level solutions using I3C and examine the improvements it can bring over I2C based solutions. Furthermore, it presents a seamless and risk free migratory path to the industry from these I2C based architectures to I3C based architectures using proven Synopsys Solutions.
  
  
• Achieving High Performance Non-Volatile Memory Access Through "Execute-In-Place" Feature (Apr. 24, 2017)
  The paper discusses about Execute In Place(XiP) feature in embedded systems implemented through the SPI protocol. Concept of XiP are explained including how it improves the overall throughput and efficiency of a system. Results are shared on the overall system throughput improvement. Further we discuss about various methods by which user can make most out of this feature.
  
  
• Allowing server-class storage in embedded applications (Apr. 19, 2017)
  In this article, a new way to implement high performance data storage is presented, allowing the use of server-class storage technology in an embedded environment.
  
  
• A 4-MHz parameterized Logarithm-Square Root IP-Core (Mar. 27, 2017)
  Abstract Logarithms and square root are non-elementary operations frequently used in digital signal processing. In this work, implementation and design of an IP-Core to compute square root and multibase logarithm is presented. The design is parameterized in fixed point notation achieving a low arithmetic error even when irrational numbers are being calculated. The module was synthesized in ASIC using FSC0G_D_GENERIC_CORE from UMC and in FPGA occupying 518 logic elements and two DSP blocks for multiplication.
  
  
• Can 10 Gbps Ethernet be an Embedded Design Solution? (Mar. 21, 2017)
  10 Gbps Ethernet (10GbE) has established itself as the standard way to connect server cards to the top-of-rack (ToR) switch in data-center racks. So what’s it doing in the architectural plans for next-generation embedded systems? It is a tale of two separate but connected worlds.
  
  
• Reusable Verification Model for Motion estimation Algorithm (Mar. 20, 2017)
  Increasing functionalities of application specific integrated circuits (ASIC) require rather more efficient verification methods. In this paper, a novel verification model (VM) for low complexity motion estimation (ME) hardware architecture used in a video encoder is proposed.
  
  
• An introduction to ARM Cortex-M0 DesignStart (Mar. 09, 2017)
  The availability of the ARM Cortex-M0 processor within ARM’s DesignStart portal makes designing and prototyping a Cortex-M0 based system-on-chip (SoC) much easier. Quick and free-of-charge access to one of the most licensed Cortex-M processors speeds up the development and validation of new, custom SoCs that will enable the growth of smart connected devices.
  
  
• Safety Verification and Optimization of Automotive Ethernet Using Dedicated SoC FIT Rates (Mar. 09, 2017)
  This article explains a new holistic methodology that combines analytic methodologies such as FMEDA with simulation-based methodologies to significantly reduce the safety verification effort and achieve faster product certification. Automated fault injection is a well-established test method used to verify the correct implementation of safety mechanisms and to get a much more realistic estimation of the FIT rates.
  
  
• Making Better Front-End Architectural Choices Avoids Back-End Timing Closure Issues (Mar. 01, 2017)
  Today’s SoC architectures are so complex that they are creating rifts between design teams in any given project. For example, when architects decide on the functionality and the underlying data flow of a design during the front-end of the chip design process, they often have little preconception of the myriad timing closure challenges that get handed to synthesis place and route teams during the back-end of the processes.
  
  
• Hybrid Hardware Architecture for Low Complexity Motion Estimation Algorithm (Feb. 13, 2017)
  Nowadays hybrid hardware architecture (HHA) becomes increasingly popular in embedded systems (ES). In this paper HHA is presented for low bit depth motion estimation (ME) algorithm. Intellectual property (IP) core is designed for ME algorithm by using field programmable gate array (FPGA) and this IP is integrated with processor system (PS) to investigate its performance in an ES. Designed ME based IP has data bus of size 32bits and is working properly up to 200 MHz. Experiments show that the HHA is integrated successfully and gives expected results in real time.
  
  
• Configurable Microprocessor for Life Essential Devices (Feb. 06, 2017)
  This paper will explore how processors have evolved with attributes such as configurability and extensibility to enable the next generation of electronics.
  
  
• A Review Paper on CMOS, SOI and FinFET Technology (Feb. 01, 2017)
  In 1958, the first integrated circuit flip-flop was built using two transistors at Texas Instruments. The chips of today contain more than 1 billion transistors. The memory that could once support an entire company’s accounting system is now what a teenager carries in his smartphone. This scale of growth has resulted from a continuous scaling of transistors and other improvements in the Silicon manufacturing process.
  
  
• Electronic Circuit Design for RF Energy Harvesting using 28nm FD-SOI Technology (Jan. 27, 2017)
  A design of voltage doubler circuit has been studied in context of electromagnetic energy harvesting using 28 nm FD-SOI technology. After analysis of the operating constraints of the circuit, the choice was made in favour of NLVT transistor configured as a diode. The design and optimization of the circuit is presented as well as the influence of the polarization of the substrate.
  
  
• A Cost-Effective Reuse Method of Off-the-Shelf MIMO Wireless LAN IPs with a Nested Spatial Mapping (Jan. 23, 2017)
  This paper presents a spatial mapping which turns dual data streams of MIMO system into an equivalent single stream. It is achieved by shrinking the constellation of the secondary stream into that of the primary data stream so that the primary one can be decoded even with a simple SISO de-mapper.
  
  
• Turning cars into mobile devices: MIPI (Jan. 17, 2017)
  Everyone remembers their first car – how you could go where you wanted to go, moving faster and going longer distances – you were mobile. Yes, our cars made us mobile, but today’s cars are becoming mobile devices themselves.
  
  
• Embedded FPGA: Changing the Way Chips Are Designed (Jan. 09, 2017)
  One of the most critical problems chip designers face today is having to reconfigure RTL at any point in the design process, even in-system. Unfortunately, chip designers have no way of knowing if they will have to do this until it is too late. Any changes at that point end up costing millions of dollars and delaying projects by months.
  
  
• Design Considerations for High Bandwidth Memory Controller (Jan. 09, 2017)
  High Bandwidth Memory (HBM) is a high-performance 3D-stacked DRAM. It is a technology which stacks up DRAM chips (memory die) vertically on a high speed logic layer which are connected by vertical interconnect technology called TSV (through silicon via) which reduces the connectivity impedance and thereby total power consumption.
  
  
• Latch-Based RAMs and the Hidden Capacitor (Jan. 04, 2017)
  Is there a place for a volatile DRAM replacement? While the VLT as a DRAM replacement might be attractive, any success hinges on effective and innovative solutions to some major problems.
  
  
• A Flexible 200kHz-20MHz Ring Oscillator in a 40nm CMOS Technology (Dec. 12, 2016)
  In this paper, we present a flexible ring oscillator IP designed for a 40nm CMOS technology, whose oscillation frequency can be chosen from 200kHz to 20MHz. It was developed using a new design approach, in which analog IPs are designed from scratch to be flexible, employing modular blocks that can be easily customized. The IP is silicon proven. It works with a supply voltage of 1.2V and features 5% frequency accuracy, occupying an area of 0.0022mm2.
  
  
• Best insurance for your design? System performance analysis (Dec. 05, 2016)
  It sounds trite, but it’s always true: The stakes are higher in system-on-chip (SoC) design than ever. And tomorrow they’ll be even higher.
  
  
• Make SoCs flexible with embedded FPGA (Dec. 01, 2016)
  Embedding an FPGA array can add vital flexibility to SoC designs.
  
  
• Microcontroller Architects Look to Embedded FPGAs for Flexibility (Nov. 24, 2016)
  Today, microcontroller families typically have dozens of versions that have various combinations of GPIO configurations: SPIs, UARTs, I2Cs, etc. to address the needs of different customers. This requires mask changes for each version. A new version takes quarters to go through the design and verification process. Now that microcontrollers are moving to the 40nm node where mask costs are ~$1M, a new solution is required.
  
  
• Fully-programmable SoCs -- A new breed of devices (Nov. 14, 2016)
  Generally, silicon devices that process information can be classified as being either SoCs, ASICs/ASSPs, or FPGAs. It is very difficult to perform power, performance, and cost comparisons between these technologies without looking at specific applications and running benchmarks. However, it may be possible to take an application and map it to comparable devices in the three categories.
  
  
• Next-generation military radio systems (Nov. 14, 2016)
  With the technological challenges surrounding Software Defined Radio (SDR) largely overcome, the deployment of first generation sets is underway. Possible enhancements such as increasing the bandwidth while simultaneously reducing the size, weight, power, and cost of the device have yet to be developed. Beyond this, Cognitive Radio represents the next major advance in wireless technology, holding out the tantalizing promise of significantly greater spectrum utilization, however, there are some significant barriers which still must be surmounted.