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IP / SOC Products Articles

• A Flexible 200kHz-20MHz Ring Oscillator in a 40nm CMOS Technology (Dec. 12, 2016)
  In this paper, we present a flexible ring oscillator IP designed for a 40nm CMOS technology, whose oscillation frequency can be chosen from 200kHz to 20MHz. It was developed using a new design approach, in which analog IPs are designed from scratch to be flexible, employing modular blocks that can be easily customized. The IP is silicon proven. It works with a supply voltage of 1.2V and features 5% frequency accuracy, occupying an area of 0.0022mm2.
  
  
• Best insurance for your design? System performance analysis (Dec. 05, 2016)
  It sounds trite, but it’s always true: The stakes are higher in system-on-chip (SoC) design than ever. And tomorrow they’ll be even higher.
  
  
• Make SoCs flexible with embedded FPGA (Dec. 01, 2016)
  Embedding an FPGA array can add vital flexibility to SoC designs.
  
  
• Microcontroller Architects Look to Embedded FPGAs for Flexibility (Nov. 24, 2016)
  Today, microcontroller families typically have dozens of versions that have various combinations of GPIO configurations: SPIs, UARTs, I2Cs, etc. to address the needs of different customers. This requires mask changes for each version. A new version takes quarters to go through the design and verification process. Now that microcontrollers are moving to the 40nm node where mask costs are ~$1M, a new solution is required.
  
  
• Do SoC Architects Have to Get Physical? (Nov. 14, 2016)
  With the rapid adoption of the 16/14nm FinFET semiconductor manufacturing processes, the SoC architect’s job is becoming more difficult.
  
  
• Fully-programmable SoCs -- A new breed of devices (Nov. 14, 2016)
  Generally, silicon devices that process information can be classified as being either SoCs, ASICs/ASSPs, or FPGAs. It is very difficult to perform power, performance, and cost comparisons between these technologies without looking at specific applications and running benchmarks. However, it may be possible to take an application and map it to comparable devices in the three categories.
  
  
• Next-generation military radio systems (Nov. 14, 2016)
  With the technological challenges surrounding Software Defined Radio (SDR) largely overcome, the deployment of first generation sets is underway. Possible enhancements such as increasing the bandwidth while simultaneously reducing the size, weight, power, and cost of the device have yet to be developed. Beyond this, Cognitive Radio represents the next major advance in wireless technology, holding out the tantalizing promise of significantly greater spectrum utilization, however, there are some significant barriers which still must be surmounted.
  
  
• A Look at New Open Standards to Improve Reliability and Redundancy of Automotive Ethernet (Nov. 10, 2016)
  To meet the safety and deterministic latency requirements for controlling a car, a new set of open standards is being developed, collectively referred to as “Time Sensitive Networking,” or TSN. These improve the reliability, timing, redundancy, and failure detection ability of Ethernet to the level where it can be applied throughout an automobile. This article describes how Cadence has addressed the hardware requirements of TSN in its Automotive Ethernet Media Access Controller (MAC).
  
  
• Adaptive Rate Control Algorithm (Oct. 31, 2016)
  Ethernet over the last few years has evolved to provide high bandwidth over the aggregate Gigabit link. Next generation telecommunication networks are also shifting towards packet processed network which is enveloped by Ethernet. Citing higher demand for faster and wider Ethernet network, it has become absolutely eminent to study factors holding bandwidth efficiencies of these networks.
  
  
• Pairing Sensitive RF with Voltage Regulators for Noise-Free IoT Modules (Oct. 24, 2016)
  This article presents the challenge of pairing an RF analog circuit with the appropriate inductor-based embedded Switching Regulator (namely eSR, equivalent to on-board DC/DC) allowing to meet both the power efficiency requirements and the module performance level at the same time.
  
  
• Mission Critical in Auto SoC: Interconnect IP (Oct. 24, 2016)
  The average number of IP cores integrated into automotive SoCs is growing from about 20 today to more than 100 within the next five to ten years.
  
  
• The basics of Bluetooth Low Energy (BLE) (Oct. 17, 2016)
  Bluetooth technology has revolutionized wireless communications between devices with its ubiquitous and simple characteristics. It allows devices to communicate without cables while maintaining high levels of security. Because of its low power and low cost, Bluetooth has played a pivotal role in the evolution of applications from high-speed automotive devices to complex medical devices.
  
  
• Power Tips: USB Power Delivery for Automotive Systems (Oct. 14, 2016)
  The new USB Type-C standard has a power delivery portion that could enable portable devices to charge faster.
  
  
• Timing Closure in the FinFET Era (Oct. 10, 2016)
  Achieving system-on-chip (SoC) timing closure is a major obstacle in the FinFET era. Even though designers can now use faster transistors that consume and leak less power than before, FinFET technology does not address the on-chip communications infrastructure or metal line resistance/capacitance issues that negatively impact timing closure.
  
  
• Providing USB Type-C connectivity - What you need to know (Oct. 06, 2016)
  USB Type-C promises to be the answer to all our high-speed serial connectivity dreams, and more. Headlines have trumpeted its higher speeds and an increased power delivery capability, but what has probably captured most people’s attention is the fully reversible connector design, which is neither keyed nor needs different connectors at opposite of a cable.
  
  
• Learning how to learn: Toddlers vs. neural networks (Sep. 28, 2016)
  It's undeniable that machine learning has made enormous progress over the past few years: from amazing artificial intelligence accomplishments like defeating a top ranking player at the ancient and complex game of Go, to simple everyday uses like auto-tagging personal photo collections.
  
  
• A Virtual Reality Camera Design with 16 Full HD Video Inputs Sharing a Single DRAM Chip (Sep. 05, 2016)
  This paper will describe a realistic design that allows the real time H.264 compression of 16 full HD (1080p@30) video streams, using both I and P frames, sharing the bandwidth of a single DDR3 DRAM chip with 16 bit data bus. This can be achieved thanks to Ocean Logic's proprietary Compressed Frame Store (CFS) technology that allows perfect reconstruction of the compressed frame store data with compression ratios of 10-20:1.
  
  
• Resets in FPGA & ASIC control and data paths (Sep. 05, 2016)
  Reset is an important mechanism to bring a digital system into a known state. The need for reset is governed by the system design and application, and various data and control paths are designed to use a reset signal. Flip-flops in the control path should have reset parameters to bring the system to a known state, while one can usually do without reset in the data path. Let’s discuss various use cases of resets in ASICs and FPGAs.
  
  
• ARM intrusive debugging for post-silicon SoC validation (Aug. 31, 2016)
  Debugging large RTL projects has become increasingly complex. With different types of applications evolving, there is a need for different ways to enable debug hooks in every application. Although the debug architecture of the SOC is at par with its complex design to make non-intrusive debugs easy, but there are multiple scenarios which require intrusive debugging. This article compiles a few scenarios which depict the use of intrusive debugging for validation of an SOC.
  
  
• LTE Single Carrier DFT: Faster Circuits with Reduced FPGA LUT/Register Usage (Aug. 22, 2016)
  Given the prominence of the LTE protocol in wireless devices, it is surprising that there are very few DFT FPGA circuit implementations from which to choose. This is likely due to the complexity of the circuit, which must accommodate run-time choice of many and large non-power-of-two transforms, requiring multiple radices for efficient DFT calculation.
  
  
• Automotive Is the New Black (Aug. 12, 2016)
  If you are designing a tailored automotive chip but new to the market, here's a newbie's guide to selecting processor IP for safety-critical applications.
  
  
• Think Big for Ultra-Low Power IoT SoCs (Aug. 04, 2016)
  Some of the best ideas in creating breakthrough IoT innovation could be gleaned from the design of much larger SoCs.
  
  
• Darwin Comes to Cable (Jul. 28, 2016)
  Pause a moment, if you will, to consider the plight of the oft-reviled cable television providers. At their roots, these companies operated essentially unidirectional networks of coaxial cable for distributing analog video signals to homes. That was then.
  
  
• Choosing a mobile-storage interface: eMMC or UFS (Jul. 26, 2016)
  It is easy to forget just how rapidly the mobile landscape has evolved. Consider that just twelve short years ago, the Motorola Razr was released. With a 0.3-megapixel camera, a 176×220 screen, and five megabytes of embedded storage, this sleek feature phone was a global sensation, with 110 million devices sold worldwide.
  
  
• Setting up secure VPN connections with cryptography offloaded to your Altera SoC FPGA (Jul. 11, 2016)
  In this white paper, we’ll explain the benefits of offloading cryptography routines to hardware. As an example platform, we consider the Cyclone® V SoC device, an Altera® FPGA. Key here is selecting the right IP blocks and installing the appropriate Linux drivers that drive the hardware and allow for an easy integration in your application. Next to being more secure, hardware cryptography is also much faster. A comparison of hardware and software security routines on the Cyclone V SoC shows a gain of 30X for typical Ethernet packets of 1.5 Kbytes.
  
  
• Synchronizing sample clocks of a data converter array (Jul. 01, 2016)
  This article provides a real-life case study of how to build a flexible and re-programmable clock expansion network, that maintains not only an excellent phase noise/jitter performance, but also passes-on the required synchronization information from the 1st device of the clock tree to the last one with deterministic control.
  
  
• Easing Heterogeneous Cache Coherent SoC Design using Arteris' Ncore Interconnect (Jun. 20, 2016)
  Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and network-on-a-chip (NoC) technology are the first step, giving architects IP to efficiently connect compute processing elements as different as CPUs, GPUs, and DSPs. Hardware IP to enable coherent communication between different types of compute engines is the next step. This white paper describes how Arteris’ Ncore IP can help architects design processors fully supporting coherency between heterogeneous elements.
  
  
• What's in the Future for High-Speed SerDes? (Jun. 16, 2016)
  High-speed SerDes interfaces are the gateway for data traffic and analysis on the cloud. End-users want a faster connection to their data. They want to download and stream HD movies as fast as possible. They also want to seamlessly share huge databases. This need for speed directly drives SerDes innovation. In the datacenter market and in the enterprise market, it’s extremely important to have a fast connection.
  
  
• Fronthaul Evolution Toward 5G: Standards and Proof of Concepts (Jun. 13, 2016)
  This paper will help to navigate through the key concepts of packet based Fronthaul and discuss the implications of the adoption of latest Time-Sensitive-Network (TSN) IEEE 802.1CM standard, the IEEE P1904.3 Radio over Ethernet (RoE) standard and latest Next Generation Fronthaul Interface, (NGFI) IEEE P1914.1 initiatives. Finally, a look at the PoC platforms enabled by Xilinx technology and IP offering from Comcores will be offered.
  
  
• Lossless Medical Video Compression Using HEVC (Jun. 06, 2016)
  This paper outlines lossless encoding mode of HEVC and how using lossless encoding mode, compression ratio of more than 2 (2:1) can be achieved.